參數(shù)資料
型號: 73S8014RN-ILR/F
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 模擬信號調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, PDSO20
封裝: LEAD FREE, SOP-20
文件頁數(shù): 10/28頁
文件大?。?/td> 389K
代理商: 73S8014RN-ILR/F
73S8014RN Data Sheet
DS_8014RN_014
18
Rev. 1.0
3.8
Deactivation Sequence
Deactivation is initiated either by the system controller by setting the CMDVCC high, or automatically in the event of
hardware faults. Hardware faults are over-current, VDD fault, VCC fault, and card extraction during the session.
The following steps show the deactivation sequence and the timing of the card control signals when the system
controller sets the CMDVCC high or OFF goes low due to a fault or card removal:
-
RST goes low at the end of t1.
-
CLK is set low at the end of t2.
-
I/O goes low at the end of t3. Out of reception mode.
-
VCC is shut down at the end of time t4. After a delay t5 (discharge of the VCC capacitor), VCC is low.
RST
CLK
I/O
VCC
t
1
t
2
t
3
t
4
t
5
CMDVCC
-- OR--
OFF
t1 = > 0.5μs, timing by 1.5MHz internal Oscillator
t2 = > 7.5μs
t3 = > 0.5μs
t4 = > 0.5μs
t5 = depends on VCC filter capacitor.
For NDS application, CF=1μF makes t1 + t2 + t3 + t4 + t5 < 250μs
Figure 6: Deactivation Sequence
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