參數(shù)資料
型號: 73S8014BN-IL/F
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 模擬信號調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, PDSO20
封裝: ROHS COMPLIANT, SOP-20
文件頁數(shù): 7/29頁
文件大?。?/td> 345K
代理商: 73S8014BN-IL/F
DS_8014BN_057
73S8014BN Data Sheet
Rev. 1.0
15
3.2
System Controller Interface
Three digital inputs allow direct control of the card interface by the host. The 73S8014BN is controlled as follows:
Pin
CMDVCC: When asserted low, starts an activation sequence. When deasserted high, starts deactivation
sequence.
Pin RSTIN: Controls the card RST signal (when enabled by the sequencer) while the card is activated and the
power-down mode when the card is not activated.
Pin 5V/
3V: Defines the card V
DD voltage according to Table 8.
Table 8: VCC Voltage Logic Table
CONTROL PINS
VCC
VOLTAGE
(V)
NOTES
CMDVCC
5V/
3V
1
x
0
Off
1
5
5V/
3V must be stable for at least 1
s before assertion of
CMDVCC and held high until deassertion of CMDVCC.
0
3
5V/
3V must be stable for at least 1
s before assertion of
CMDVCC and held low until deassertion of CMDVCC.
1.8
Must be asserted low within 400ns of each other to generate
1.8V and held low until assertion of
CMDVCC.
The
OFF digital output reports status back to the host. See the Fault Detection and OFF section for details on the
operation of the
OFF output.
Note: 5V/
3V should not change during a card session. Doing so does not change the voltage on V
CC
during that session, but if it is changed, the 5V/
3V must be taken high outside the current card session
and before beginning the next card session. Otherwise, the next card session may not power up to the
selected VCC voltage.
3.3
Power-Down Mode
The 73S8014BN includes a power-down mode to greatly reduce the power consumption on the VDD and VPC
supplies when the smart card interface is deactivated. The power-down mode shuts down the crystal oscillator
and other internal circuits to save power. When the power-down mode is released, the oscillator is restarted. It
requires some time to start up and stabilize. During this time, the
OFF output goes low (if a card is inserted) and is
held low until the oscillator stabilizes, and then the
OFF output goes high to indicate that the device is ready to
activate the card.
The power-down mode is initiated when RSTIN,
CMDVCC, and 5V/3V are all logic-high for more than 2ms. The
power-down mode is released immediately by bringing RSTIN low. This action forces the
OFF output low for
approximately 5ms to 7ms to allow the oscillator to start up and stabilize. This action informs the host that the
73S8014BN is busy and should not be activated while the
OFF output is low. This ensures a proper activation
sequence after coming out of power-down.
The card-detection logic on the PRES input remains active in power-down mode. The card status is reported on
OFF.
Note: The
CMDVCC and 5V/3V inputs have no effect when exiting power-down. Bringing RSTIN low is the only
way to exit power-down.
Figure 4 shows the power-down mode control timing with PRES debounce. See Section 3.9 for a full description
of the PRES debounce behavior.
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