參數(shù)資料
型號(hào)： 73S8010R-IMR/F
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, QCC32
封裝： 5 X 5 MM, 0.80 MM HEIGHT, LEAD FREE, QFN-32
文件頁(yè)數(shù)： 14/25頁(yè)
文件大?。?/td> 336K
代理商： 73S8010R-IMR/F
DS_8010R_022
73S8010R Data Sheet
Rev. 1.6
21
3.10 Warm Reset
The 73S8010R automatically asserts a warm reset to the card when instructed through bit 1 of the I
2C
Control register (bit Warm Reset). The warm reset length is automatically defined as 42,000 card clock
cycles. The Warm Reset bit is automatically reset when the card starts answering or when the card is
declared mute.
Figure 11: Warm Reset Operation
3.11 I/O Circuitry and Timing
The states of the I/O, AUX1, and AUX2 pins are low after power-on-reset and they are high when the
activation sequencer enables the I/O reception state. See Section 3.7 Activation Sequence for more
details on when the I/O reception is enabled. The states of the I/OUC, AUX1UC, and AUX2UC are high
after power on reset.
When the control I/O enable bit (bit 7) of the control register is set, the first I/O line on which a falling edge
is detected becomes the input I/O line and the other becomes the output I/O line. When the input I/O line
rising edge is detected, then both I/O lines return to their neutral state. The delay between these signals
is shown in Figure 12.
IO
IOUC
t
IO_HL
t
IO_LH
t
IOUC_HL
t
IOUC_LH
Delay from I/O to I/OUC:
tIO_HL = 100ns
tIO_LH = 25ns
Delay from I/OUC to I/O:
tIOuc_HL = 100ns
tIOUC_LH = 25ns
Figure 12: I/O Timing Diagram
Warm Reset
(bit 1)
RST
t
1
t
2
t
1 > 1.5s, Warm Reset Starts
t
2 = 42000 card clock cycles, End of Warm Reset
t
3
t
3 = Resets Warm Reset bit 1 when detected ATR or Mute
IO
相關(guān)PDF資料
PDF描述
73S8010R-ILR/F SPECIALTY ANALOG CIRCUIT, PDSO28
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73S8010R-ILR SPECIALTY ANALOG CIRCUIT, PDSO28
73S8010R-IMR SPECIALTY ANALOG CIRCUIT, QCC32
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