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| 型號(hào)： | 73S1209F-68IMR/F |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY MANAGEMENT CKT, QCC68 |
| 封裝： | LEAD FREE, QFN-68 |
| 文件頁(yè)數(shù)： | 68/123頁(yè) |
| 文件大?。?/td> | 1385K |
| 代理商： | 73S1209F-68IMR/F |
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DS_1209F_004
73S1209F Data Sheet
Rev. 1.2
49
1.7.7 User (USR) Ports
The 73S1209F includes 9 pins of general purpose digital I/O (GPIO). On reset or power-up, all USR pins
are inputs until they are configured for the desired direction. The pins are configured and controlled by
the USR and UDIR SFRs. Each pin declared as USR can be configured independently as an input or
output with the bits of the UDIRn registers. Table 48 lists the direction registers and configurability
associated with each group of USR pins. USR pins 0 to 7 are multiple use pins that can be used for
general purpose I/O, external interrupts and timer control.
Table 49 shows the configuration for a USR pin through its associated bit in its UDIR register. Values
read from and written into the GPIO ports use the data registers USR70 and USR8. Note: After reset, all
USR pins are defaulted as inputs and pulled up to VDD until any write to the corresponding UDIR register
is performed. This insures all USR pins are set to a known value until set by the firmware. Unused USR
pins can be set for output if unused and unconnected to prevent them from floating. Alternatively, unused
USR pins can be set for input and tied to ground or VDD.
Table 48: Direction Registers and Internal Resources for DIO Pin Groups
USR Pin Group
Type
Direction
Register
Name
Direction
Register
(SFR)
Location
Data
Register
Name
Data
Register
(SFR)
Location
USR_0…USR_7
Multi-use
UDIR70
0x91 [7:0]
USR70
0x90 [7:0]
USR_8
GPIO only
UDIR8
0xA1 [0]
USR8
0xA0 [0]
Table 49: UDIR Control Bit
UDIR Bit
0
1
USR Pin
Function
output
input
USR [7:0] pins. Each of the USR [7:0] pins can be configured as GPIO or individually be assigned an
internal resource such as an interrupt or a timer/counter control. Each of the four registers contains two
3-bit configuration words named UxIS (where x corresponds to the USR pin). The control resources
selectable for the USR pins are listed in Table 74 through Table 78. If more than one input is connected
to the same resource, the resources are combined using a logical OR.
Table 50: Selectable Controls Using the UxIS Bits
UxIS Value
Resource Selected for USRx Pin
0
None
1
None
2
T0 (counter0 gate/clock)
3
T1 (counter1 gate/clock)
4
Interrupt 0 rising edge/high level on USRx
5
Interrupt 1 rising edge/high level on USRx
6
Interrupt 0 falling edge/low level on USRx
7
Interrupt 1 falling edge/low level on USRx
Note: x denotes the corresponding USR pin. Interrupt edge or level control is assigned in the IT0 and IT1
bits in the TCON register.
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| 73S1209F-68M/F/P1 | 功能描述:8位微控制器 -MCU Contained 80515-SoC Serial Hst Interface RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| 73S1209F-EB | 功能描述:開發(fā)板和工具包 - 8051 73S1209F Eval Brd (Doc. Cd, Cable) RoHS:否 制造商:Silicon Labs 產(chǎn)品:Development Kits 工具用于評(píng)估:C8051F960, Si7005 核心: 接口類型:USB 工作電源電壓: |
| 73S1209F-IM44 DK | 制造商:Maxim Integrated Products 功能描述:Development Boards & Kits - 8051 73S1209F Dev Kit Eval Bd Ice Cable Cd |
| 73S1209F-IM44 EB | 制造商:Maxim Integrated Products 功能描述:Development Boards & Kits - 8051 73S1209F Eval Brd Eval Bd Doc Cd Cable |
| 73S1209F-IM68 DK | 制造商:Maxim Integrated Products 功能描述:Development Boards & Kits - 8051 73S1209F Dev Kit Eval Bd Ice Cable Cd |
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