參數(shù)資料
型號： 73M2910L-IG
英文描述： Microcontroller
中文描述： 微控制器
文件頁數(shù)： 18/41頁
文件大?。?/td> 509K
代理商： 73M2910L-IG
73M2910L
Microcontroller
HDLC STATUS REGISTER (HSTAT) SFR ADDRESS 0C3h
(continued)
18
BIT 4 RX Overrun
When bit 4 is set, a receive overrun condition has been detected. This is a condition where the HDLC has
received a new byte, but the last received data byte has not yet been read from the RX Data Register. As soon
as a new data byte has been received in an eight-bit serial register, it is loaded into the RX Data Register and a
new RX data interrupt is generated. If this interrupt is not serviced by reading the RX Data Register during the
time another new data byte is received, the RX overrun status bit will be set. The new received data will not
overwrite the older unread data.
Bit 4 will by cleared upon a reset and is cleared by a read of the HDLC Stat Register.
BIT 3 Invalid Flag
When bit 3 is set, an invalid flag has been detected. This is a condition where a 7E pattern with no inserted 0s is
detected, and this pattern did not originate on a byte boundary. Note, two consecutive flags may share a 0, so
that the second (or subsequent) flag may not appear to be on a byte boundary. This condition does not result in
an invalid flag indication.
Bit 3 will by cleared upon a reset and is cleared by a read of the HDLC Stat Register.
BIT 2 Abort Detect
When bit 2 is set, an abort condition has been detected. This is a condition where seven consecutive ones, with
no inserted zeros, are received after an active state. Bit 2 will be cleared upon a reset and is cleared by a read
of the HDLC Stat Register.
BIT 1 Idle Detect
When bit 1 is set, the first indication of an idle state is detected. An idle state is declared when 15 consecutive
ones, with no inserted zeros, are received after an active state.
Bit 1 will be cleared upon a reset and is cleared by a read of the HDLC Stat Register.
BIT 0 Flag Detect
When bit 0 is set, the HDLC has received a 7E pattern with no inserted 0’s. Bit 0 will by cleared upon a reset
and is cleared by a read of the HDLC Stat Register.
HDLC INTERRUPT ENABLE REGISTER (HIE) SFR ADDRESS 0C4h
Byte Addressable
Reset State 00h
If the bit is set, the corresponding interrupt source is enabled.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TX RDY
IE
RX RDY
IE
TX RDY
EN
RX RDY
EN
INVAL
FLG IE
ABORT
IE
IDLE
IE
FLAG
IE
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