參數(shù)資料
型號： 73M1903C-IM
廠商： TERIDIAN SEMICONDUCTOR CORP
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, QCC32
封裝： LEAD FREE, QFN-32
文件頁數(shù)： 5/45頁
文件大小： 459K
代理商： 73M1903C-IM
73M1903C
Modem Analog Front End
DATA SHEET
Page: 13 of 45
2005 TERIDIAN Semiconductor Corporation
Rev 3.4
CLOCK GENERATION
Crystal Oscillator and Prescaler NCO
The crystal oscillator operates over wide choice of crystals (from 4.9MHz to 27MHz) and it is first input to
an NCO-based prescaler (divider) prior to being passed onto an on-chip PLL. The intent of the prescaler
is to convert the crystal oscillator frequency, Fxtal, to a convenient frequency to be used as a reference
frequency, Fref, for the PLL. The NCO prescaler requires a set of three numbers to be entered through
the serial port (Pseq[7:0], Prst[2:0] and Pdvsr[2:0]. The PLL also requires 3 numbers as for programming;
Ndvsr[6:0], Nseq[7:0], and Nrst[2:0]. The following is a brief description of the registers that control the
NCOs, PLLs, and sample rates for the TERIDIAN 73M1903C IC. The tables show some examples of the
register settings for different clock and sample rates. A more detailed discussion on how these values
are derived can be found in Appendix B.
Control Register (CTRL 8): Address 08h
Reset State 00h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Pseq7
Pseq6
Pseq5
Pseq4
Pseq3
Pseq2
Pseq1
Pseq0
This corresponds to the sequence of divisor. If Prst{2:0] =0 this register is ignored.
Control Register (CTRL 9): Address 09h
Reset State 0Ah
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Prst2
Prst1
Prst0
Pdvsr4
Pdvsr3
Pdvsr2
Pdvsr1
Pdvsr0
Prst[2:0] represents the rate at which the sequence register is reset.
Pdvsr[4:0] represents the divisor.
Control Register (CTRL 10): Address 0Ah
Reset State 22h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FL
Kvco2
Kvco1
Kvco0
.Kvco2:0 represents the magnitude of Kvco associated with the VCO within PLL. This indicates the center
frequency of the VCO when the control voltage (Vc) is 1.6 Volts and the slope of the VCO freq vs. control
voltage (i.e., Kvco.). FL represents the PLL loop filter settings.
Kvco2
Kvco1
Kvco0
Fvco
Kvco
0
33 MHz
38MHz/v
0
1
36 MHz
38MHz/v
0
1
0
44 MHz
40MHz/v
0
1
48 MHz
40MHz/v
1
0
57 MHz
63MHz/v
1
0
1
61 MHz
63MHz/v
1
0
69 MHz
69MHz/v
1
73 MHz
69MHz/v
Table 3: Kvco vs. Settings at Vc=1.6V, 25°C
FL
PLLloop Filter settings
0
R1=32k,C1=100pF,C2=2.5pF
1
R1=16k, C1=100pF,C2=2.5pF
Table 4: PLL Loop Filter Settings
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