參數(shù)資料
型號(hào): 73M1903C-IM
廠商: TERIDIAN SEMICONDUCTOR CORP
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, QCC32
封裝: LEAD FREE, QFN-32
文件頁(yè)數(shù): 41/45頁(yè)
文件大?。?/td> 459K
代理商: 73M1903C-IM
73M1903C
Modem Analog Front End
DATA SHEET
Page: 5 of 45
2005 TERIDIAN Semiconductor Corporation
Rev 3.4
SERIAL INTERFACE
The serial data port is a bi-directional port that can be supported by most DSPs. The 73M1903C can be
configured either as a master or a slave of the serial interface. When the 73M1903C is configured as a
master device, it generates a serial bit clock, Sclk, from a system clock, Sysclk, which is normally an
output from an on-chip PLL that can be programmed by the user. In master mode, the serial bit clock is
always derived by dividing the system clock by 18.
The sclk rate, Fsclk, is related to the frame
synchronization rate, Fs, by the relationship Fsclk = 256 x Fs or Fs = Fsclk / 256 = Fsys / 18 / 256 = Fsys
/ 4608, where Fsys is the frequency of Sysclk. Fs is also the rate at which both transmit and receive data
bytes are sent (received) to (by) the Host. Throughout this document two pairs of sample rate, Fs, and
crystal frequency, Fxtal, will be often cited to facilitate discussions. They are:
1. Fxtal1 = 27MHz, Fs1 = 7.2kHz
2. Fxtal2 = 18.432MHz, Fs2 = 8kHz.
3. Fxtal3 = 24.576MHz, Fs3 = 9.6kHz
Upon reset, until a switch to the PLL based clock, Pllclk, occurs, the system clock will be at the crystal
frequency, Fxtal, and therefore the serial bit clock will be sclk = Fsys/18 = Fxtal/18.
Examples:
1. If Fxtal1 = 27.000MHz, then sclk=1.500MHz and Fs=sclk/256 = 5.859375kHz.
2. If Fxtal2 = 18.432MHz, then sclk=1.024MHz and Fs=sclk/256 = 4.00kHz.
3. If Fxtal3 = 24.576MHz, then sclk=1.3653MHz and Fs=sclk/256 = 5.33kHz.
When 73M1903C is programmed through the serial port to a desired Fs and the PLL has settled out, the
system clock will transition to the PLL-based clock in a glitch-less manner.
Examples:
1. If Fs1 = 7.2kHz, Fsys = 4608 * Fs = 33.1776MHz and sclk = Fsys / 18 = 1.8432MHz.
2. If Fs2 = 8.0kHz, Fsys = 4608 * Fs = 36.8640MHz and sclk = Fsys / 18 = 2.048MHz.
3. If Fs3 = 9.6kHz, Fsys = 4608 * Fs = 44.2368MHz and sclk = Fsys / 18 = 2.4576MHz.
This transition is entirely controlled by the host. Upon reset or power down of PLL and/or analog front
end, the chip will automatically run off the crystal until the host forces the transition by setting bit 7 in
control register 0Eh. The transition should be forced on or after the second Frame Synch period following
the write to a designated PLL programming register (0Dh).
When reprogramming the PLL the host should first transition the system clock to the crystal before
reprogramming the PLL so that any transients associated with it will not adversely impact the serial port
communication.
Power saving is accomplished by disabling the analog front end by clearing bit 7 of CTRL1 (address 00h),
ENFE=0.
During the normal operation, a data frame sync signal (
FS) is generated by the 73M1903C at the rate of
Fs. For every data
FS there are 16 bits transmitted and 16 bits received.
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