參數(shù)資料
型號: 72V805L15PFI9
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: FIFO
英文描述: 256 X 18 BI-DIRECTIONAL FIFO, 10 ns, PQFP128
封裝: TQFP-128
文件頁數(shù): 4/26頁
文件大?。?/td> 325K
代理商: 72V805L15PFI9
12
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
FF will go HIGH during the current clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then
FF may not change state until the next WCLK edge.
2. Select this mode by setting (
FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
WCLK
D0 - D17
WEN
FF
t CLK
t CLKH
t CLKL
t DS
tENS
t DH
tENH
tWFF
t WFF
DATA IN VALID
NO OPERATION
RCLK
SKEW1
t
(1)
REN
4295 drw 06
NOTES:
1. Single device mode (
FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0). FL, RXI, WXI should be static (tied to VCC or GND).
2. The clocks (RCLK, WCLK) can be free-running asynchronously or coincidentally.
3. After reset, the outputs will be LOW if
OE = 0 and tri-state if OE = 1.
RS
REN, WEN, LD
PAE
PAF, WXO/
HF, RXO
t RSR
Q0 - Q17
OE = 0
OE = 1
(1)
4295 drw 05
tRSS
CONFIGURATION SETTING
t RSR
FL, RXI, WXI
RCLK, WCLK
FF/IR
RSF
t
EF/OR
FWFT Mode
IDT Standard Mode
(3)
(2)
RSF
t
RSF
t
RSF
t
RSF
t
tRS
Figure 5. Reset Timing(2)
Figure 6. Write Cycle Timing with Single Register-Buffered
FF (IDT Standard Mode)
相關PDF資料
PDF描述
72V805L15PF8 256 X 18 BI-DIRECTIONAL FIFO, 10 ns, PQFP128
7305-0-15-15-47-14-04-0 BRASS, GOLD FINISH, PCB TERMINAL
7305-0-15-15-47-01-04-0 BRASS, GOLD FINISH, PCB TERMINAL
7305-0-15-01-47-27-04-0 BRASS, TIN FINISH, PCB TERMINAL
7305-0-15-01-47-14-04-0 BRASS, TIN FINISH, PCB TERMINAL
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