參數(shù)資料
型號(hào)： 72V805L15PFI9
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： FIFO
英文描述： 256 X 18 BI-DIRECTIONAL FIFO, 10 ns, PQFP128
封裝： TQFP-128
文件頁(yè)數(shù)： 14/26頁(yè)
文件大?。?/td> 325K
代理商： 72V805L15PFI9
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
21
D0 - D17
WEN
RCLK
FF
REN
tENH
Q0 - Q17
DATA READ
NEXT DATA READ
DATA IN OUTPUT REGISTER
LOW
OE
DATA WRITE
4295 drw 24
WCLK
NO WRITE
1
2
1
2
tDS
NO WRITE
tWFF
tA
tENS
tDS
tA
Wd
(1)
tENS
tSKEW1
WCLK
D0 - D17
WEN
FF
RCLK
REN
tWFF
DATAIN VALID
NO OPERATION
(1)
tSKEW1
4295 drw 25
tENH
1
2
tCLKH
tCLKL
tCLK
tDS
tDH
tENS
Figure 25. Write Cycle Timing with Double Register-Buffered
FF (IDT Standard Mode)
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
FF will go HIGH after one WCLK cycle plus tWFF. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW1, then the
FF deassertion time may be delayed an extra WCLK cycle.
2.
LD = HIGH.
3. Select this mode by setting (
FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.
Figure 24. Double Register-Buffered Full Flag Timing (IDT Standard Mode)
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
FF will go HIGH after one WCLK cycle plus tRFF. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW1. then the
FF deassertion may be delayed an extra WCLK cycle.
2.
LD = HIGH
3. Select this mode by setting (
FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.
相關(guān)PDF資料
PDF描述
72V805L15PF8 256 X 18 BI-DIRECTIONAL FIFO, 10 ns, PQFP128
7305-0-15-15-47-14-04-0 BRASS, GOLD FINISH, PCB TERMINAL
7305-0-15-15-47-01-04-0 BRASS, GOLD FINISH, PCB TERMINAL
7305-0-15-01-47-27-04-0 BRASS, TIN FINISH, PCB TERMINAL
7305-0-15-01-47-14-04-0 BRASS, TIN FINISH, PCB TERMINAL
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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