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參數(shù)資料
| 型號： | 72V3613L20PQF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | FIFO |
| 英文描述： | 64 X 36 OTHER FIFO, 12 ns, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁數(shù)： | 4/26頁 |
| 文件大?。?/td> | 263K |
| 代理商： | 72V3613L20PQF |
12
IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIALTEMPERATURERANGE
The levels applied to the port B bus-size select (SIZ0, SIZ1) inputs and the
Big-Endianselect(
BE)inputarestoredoneachCLKBLOW-to-HIGHtransition.
The stored port B bus-size selection is implemented by the next rising edge on
CLKB according to Figure 2.
Only 36-bit long-word data is written to or read from the FIFO memory on
theIDT72V3613.Bus-matchingoperationsaredoneafterdataisreadfromthe
FIFO RAM. Port B bus sizing does not apply to mail register operations.
BUS-MATCHING FIFO READS
Data is read from the FIFO RAM in 36-bit long-word increments. If a long-
word bus-size is implemented, the entire long word immediately shifts to the
FIFO output register upon a read. If byte or word size is implemented on port
B, only the first one or two bytes appear on the selected portion of the FIFO
output register, with the rest of the long word stored in auxiliary registers. In
this case, subsequent FIFO reads with the same bus-size implementation
output the rest of the long word to the FIFO output register in the order shown
by Figure 2.
EachFIFOreadwithanewbus-sizeimplementationautomaticallyunloads
datafromtheFIFORAMtoitsoutputregisterandauxiliaryregisters.Therefore,
implementinganewportBbus-sizeandperformingaFIFOreadbeforeallbytes
or words stored in the auxiliary registers have been read results in a loss of the
unread data in these registers.
When reading data from FIFO in byte or word format, the unused B0-B35
outputsareindeterminate.
BYTE SWAPPING
The byte-order arrangement of data read from the FIFO can be changed
synchronous to the rising edge of CLKB. Byte-order swapping is not available
for mail register data. Four modes of byte-order swapping (including no swap)
can be done with any data port size selection. The order of the bytes are
rearranged within the long word, but the bit order within the bytes remains
constant.
Byte arrangement is chosen by the port B Swap select (SW0, SW1) inputs
on a CLKB rising edge that reads a new long word from the FIFO. The byte
orderchosenonthefirstbyteorfirstwordofanewlongwordreadfromtheFIFO
ismaintaineduntiltheentirelongwordistransferred,regardlessoftheSW0and
SW1 states during subsequent reads. Figure 4 is an example of the byte-order
swapping available for long word reads. Performing a byte swap and bus-size
simultaneously for a FIFO read first rearranges the bytes as shown in Figure
4, then outputs the bytes as shown in Figure 2.
PORT-B MAIL REGISTER ACCESS
In addition to selecting port B bus sizes for FIFO reads, the port B bus Size
select (SIZ0, SIZ1) inputs also access the mail registers. When both SIZ0 and
SIZ1 are HIGH, the mail1 register is accessed for a port B long-word read and
the mail2 register is accessed for a port B long-word write. The mail register is
accessed immediately and any bus-sizing operation that can be underway is
unaffectedbythemailregisteraccess.Afterthemailregisteraccessiscomplete,
thepreviousFIFOaccesscanresumeinthenextCLKBcycle.Thelogicdiagram
in Figure 3 shows the previous bus-size selection is preserved when the mail
registers are accessed from port B. A port B bus-size is implemented on each
rising CLKB edge according to the states of SIZ0_Q, SIZ1_Q, and
BE_Q.
PARITY CHECKING
TheportAdatainputs(A0-A35) andportBdatainputs(B0-B35)eachhave
fourparitytreestochecktheparityofincoming(oroutgoing)data. Aparityfailure
on one or more bytes of the port A data bus is reported by a low level on the
port A Parity Error Flag (
PEFA). A parity failure on one or more bytes of the
port B data inputs that are valid for the bus-size implementation is reported by
a low level on the port B Parity Error Flag (
PEFB).OddorEvenparitychecking
can be selected, and the Parity Error Flags can be ignored if this feature is not
desired.
ParitystatusischeckedoneachinputbusaccordingtotheleveloftheOdd/
Evenparity(ODD/
EVEN)selectinput. Aparityerrorononeormorevalidbytes
of a port is reported by a LOW level on the corresponding port Parity Error Flag
(
PEFA,PEFB)output. PortAbytesarearrangedasA0-A8,A9-A17,A18-A26,
and A27-A35, and port B bytes are arranged as B0-B8, B9-B17, B18-B26, and
B27-B35,anditsvalidbytesarethoseusedinaportBbussizeimplementation.
When Odd/Even parity is selected, a port Parity Error Flag (
PEFA, PEFB) is
LOW if any byte on the port has an odd/even number of LOW levels applied
toitsbits.
The four parity trees used to check the A0-A35 inputs are shared by the
mail2registerwhenparitygenerationisselectedforport-Areads(PGA=HIGH).
WhenaportAreadfromthemail2registerwithparitygenerationisselectedwith
CSA LOW, ENA HIGH, W/RA LOW, MBA HIGH, and PGA HIGH, the port A
Parity Error Flag (
PEFA) is held HIGH regardless of the levels applied to the
A0-A35 inputs. Likewise, the parity trees used to check the B0-B35 inputs are
shared by the mail1 register when parity generation is selected for port B reads
(PGB=HIGH). WhenaportBreadfromthemail1registerwithparitygeneration
isselectedwith
CSBLOW,ENBHIGH,W/RBLOW,bothSIZ0andSIZ1HIGH,
and PGB HIGH, the port B Parity Error Flag (
PEFB) is held HIGH regardless
of the levels applied to the B0-B35 inputs.
PARITY GENERATION
A HIGH level on the port A Parity Generate select (PGA) or port B Parity
Generateselect(PGB)enablestheIDT72V3613togenerateparitybitsforport
reads from a FIFO or mailbox register. Port A bytes are arranged as A0-A8,
A9-A17,A18-A26,andA27-A35,withthemostsignificantbitofeachbyteused
as the parity bit. Port B bytes are arranged as B0-B8, B9-B17, B18-B26, and
B27-B35,withthemostsignificantbitofeachbyteusedastheparitybit. Awrite
to a FIFO or mail register stores the levels applied to all nine inputs of a byte
regardless of the state of the Parity Generate select (PGA, PGB) inputs. When
data is read from a port with parity generation selected, the lower eight bits of
each byte are used to generate a parity bit according to the level on the ODD/
EVENselect. Thegeneratedparitybitsaresubstitutedforthelevelsoriginally
written to the most significant bits of each byte as the word is read to the data
outputs.
Parity bits for FIFO data are generated after the data is read from the FIFO
memoryandbeforethedataiswrittentotheoutputregister. Therefore,theport
AParityGenerateselect(PGA)andOdd/Evenparityselect(ODD/
EVEN)have
setupandholdtimeconstraintstotheportAClock(CLKA)andtheportBParity
Generate select (PGB) and ODD/
EVEN select have setup and hold time
constraints to the port B Clock (CLKB). These timing constraints only apply for
a rising clock edge used to read a new long word to the FIFO output register
(see Figure 16 and 17).
The circuit used to generate parity for the mail1 data is shared by the port
B bus (B0-B35) to check parity and the circuit used to generate parity for the
mail2 data is shared by the port A bus (A0-A35) to check parity. The shared
paritytreesofaportareusedtogenerateparitybitsforthedatainamailregister
when the port Chip Select (
CSA, CSB) is LOW, Enable (ENA, ENB) is HIGH,
andWrite/Readselect(W/
RA,W/RB)inputisLOW,themailregisterisselected
(MBA HIGH for port A; both SIZ0 and SIZ1 are HIGH for port B), and port Parity
Generate select (PGA, PGB) is HIGH. Generating parity for mail register data
does not change the contents of the register. Parity Generation timing, when
reading from a mail register, can be found in Figure 18 and 19.
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| 72V3614L12PF8 | 功能描述:IC FIFO 64X36X2 12NS 120QFP 制造商:idt, integrated device technology inc 系列:72V 包裝:帶卷（TR） 零件狀態(tài):過期 存儲容量:4.5K（64 x 36 x 2） 功能:同步 數(shù)據(jù)速率:83MHz 訪問時間:8ns 電壓 - 電源:3 V ~ 3.6 V 電流 - 電源（最大值）:500mA 總線方向:雙向 擴充類型:寬 可編程標志支持:是 中繼能力:無 FWFT 支持:無 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 供應(yīng)商器件封裝:120-TQFP（14x14） 標準包裝:750 |
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