參數(shù)資料
型號: 72V3613L20PQF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: FIFO
英文描述: 64 X 36 OTHER FIFO, 12 ns, PQFP132
封裝: PLASTIC, QFP-132
文件頁數(shù): 1/26頁
文件大?。?/td> 263K
代理商: 72V3613L20PQF
3.3 VOLT CMOS CLOCKED FIFO WITH
BUS-MATCHINGAND BYTE SWAPPING
64 x 36
IDT72V3613
1
MAY 2003
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4661/1
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
FEATURES:
64 x 36 storage capacity FIFO buffering data from Port A to Port B
Supports clock frequencies up to 83MHz
Fast access times of 8ns
Free-running CLKA and CLKB may be asynchronous or
coincident (permits simultaneous reading and writing of data on
a single clock edge)
Mailbox bypass registers in each direction
Dynamic Port B bus sizing of 36 bits (long word), 18 bits (word),
and 9 bits (byte)
Selection of Big- or Little-Endian format for word and byte bus
sizes
Three modes of byte-order swapping on Port B
Programmable Almost-Full and Almost-Empty flags
Microprocessor interface control logic
FF , AF flags synchronized by CLKA
EF , AE flags synchronized by CLKB
Passive parity checking on each Port
Parity Generation can be selected for each Port
Available in 132-pin plastic quad flat package (PQF), or space
saving 120-pin thin quad flat package (TQFP)
Pin and functionally compatible version of the 5V operating
IDT723613
Industrial temperature range (–40
°°°°°C to +85°°°°°C) is available
DESCRIPTION:
The IDT72V3613 is a pin and functionally compatible version of the
IDT723613, designed to run off a 3.3V supply for exceptionally low-power
consumption. This device is a monolithic, high-speed, low-power, CMOS
synchronous (clocked) FIFO memory which supports clock frequencies up to
83MHzandhasread-accesstimesasfastas8ns.The64x36dual-portSRAM
FIFO buffers data from port A to port B. The FIFO operates in IDT Standard
modeandhasflagstoindicateemptyandfullconditions,andtwoprogrammable
flags, Almost-Full (
AF) and Almost-Empty (AE), to indicate when a selected
number of words is stored in memory. FIFO data on port B can be output in 36-
bit,18-bit,and9-bitformatswithachoiceofBig-orLittle-Endianconfigurations.
FUNCTIONAL BLOCK DIAGRAM
Mail 2
Register
Mail 1
Register
Input
Register
Output
Register
64 x 36
Write
Pointer
Read
Pointer
Status Flag
Logic
CLKA
CSA
W/
RA
ENA
MBA
Port-A
Control
Logic
Device
Control
RST
PEFA
MBF2
Port-B
Control
Logic
MBF1
EF
AE
36
B0 - B35
FF
AF
FS0
FS1
4661 drw 01
Programmable
Flag Offset
Registers
A0 - A35
Parity
Gen/Check
Parity
Generation
FIFO
ODD/
EVEN
PGA
Parity
Gen/Check
PGB
PEFB
36
RAM ARRAY
64 x 36
Bus-Matching
and
Byte
Swapping
Output
Register
CLKB
CSB
W/
RB
ENB
BE
SIZ0
SIZ1
SW0
SW1
Port-B
Control
Logic
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7305-0-15-01-47-01-10-0 BERYLLIUM COPPER, TIN LEAD (300) OVER NICKEL FINISH, PCB TERMINAL
7305-0-15-15-47-27-10-0 BERYLLIUM COPPER, GOLD (30) OVER NICKEL FINISH, PCB TERMINAL
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