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參數(shù)資料
| 型號(hào)： | 72V01L25J8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | FIFO |
| 英文描述： | 512 X 9 OTHER FIFO, 25 ns, PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 142K |
| 代理商： | 72V01L25J8 |
4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V01/72V02/72V03/72V04/72V05/72V06 3.3V ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 and 16,384 x 9
SIGNAL DESCRIPTIONS
INPUTS:
DATA IN (D0 – D8)
Data inputs for 9-bit wide data.
CONTROLS:
RESET (
RS)
Reset is accomplished whenever the Reset (
RS) input is taken to a LOW
state. During reset, both internal read and write pointers are set to the first
location. A reset is required after power up before a write operation can take
place. Both the Read Enable (
R) and Write Enable (W) inputs must be
in the HIGH state during the window shown in Figure 2, (i.e., tRSS
before the rising edge of
RS ) and should not change until tRSR after
the rising edge of
RS. Half-Full Flag (HF) will be reset to HIGH after
Reset (
RS).
WRITE ENABLE (
W)
A write cycle is initiated on the falling edge of this input if the Full Flag (
FF)
isnotset. Datasetupandholdtimesmustbeadheredtowithrespecttotherising
edge of the Write Enable (
W). DataisstoredintheRAMarraysequentiallyand
independently of any ongoing read operation.
After half of the memory is filled and at the falling edge of the next write
operation, the Half-Full Flag (
HF)willbesettoLOWandwillremainsetuntilthe
difference between the write pointer and read pointer is less than or equal to
one half of the total memory of the device. The Half-Full Flag (
HF)isthenreset
by the rising edge of the read operation.
To prevent data overflow, the Full Flag (
FF) will go LOW, inhibiting further
write operations. Upon the completion of a valid read operation, the Full Flag
(
FF) will go HIGH after tRFF, allowing a valid write to begin. When the FIFO
is full, the internal write pointer is blocked from
W,soexternalchangesinWwill
not affect the FIFO when it is full.
READ ENABLE (
R)
A read cycle is initiated on the falling edge of the Read Enable (
R)provided
theEmptyFlag(
EF)isnotset.ThedataisaccessedonaFirst-In/First-Outbasis,
independent of any ongoing write operations. After Read Enable (
R) goes
HIGH,theDataOutputs(Q0– Q8)willreturntoahighimpedanceconditionuntil
thenextReadoperation. WhenalldatahasbeenreadfromtheFIFO,theEmpty
Flag (
EF)willgoLOW,allowingthe“final”readcyclebutinhibitingfurtherread
operations with the data outputs remaining in a high impedance state. Once a
validwriteoperationhasbeenaccomplished,theEmptyFlag(
EF)willgoHIGH
aftertWEFandavalidReadcanthenbegin. WhentheFIFOisempty,theinternal
read pointer is blocked from
RsoexternalchangesinRwillnotaffecttheFIFO
when it is empty.
FIRST LOAD/RETRANSMIT (
FL/RT)
This is a dual-purpose input. In the Depth Expansion Mode, this pin is
groundedtoindicatethatitisthefirstloaded(seeOperatingModes).IntheSingle
Device Mode, this pin acts as the retransmit input. The Single Device Mode is
initiated by grounding the Expansion In (
XI).
These FIFOs can be made to retransmit data when the Retransmit Enable
control(
RT)inputispulsedLOW. Aretransmitoperationwillsettheinternalread
pointer to the first location and will not affect the write pointer. Read Enable (
R)
andWriteEnable(
W)mustbeintheHIGHstateduringretransmit.Thisfeature
is useful when less than 512/1,024/2,048/4,096/8,192/16,384 writes are
performed between resets. The retransmit feature is not compatible with the
Depth Expansion Mode and will affect the Half-Full Flag (
HF), depending on
the relative locations of the read and write pointers.
EXPANSION IN (
XI)
This input is a dual-purpose pin. Expansion In (
XI) is grounded to indicate
an operation in the single device mode. Expansion In (
XI) is connected to
Expansion Out (
XO) of the previous device in the Depth Expansion or Daisy
Chain Mode.
OUTPUTS:
FULL FLAG (
FF)
The Full Flag (
FF)willgoLOW,inhibitingfurtherwriteoperation,whenthe
writepointerisonelocationlessthanthereadpointer,indicatingthatthedevice
is full. If the read pointer is not moved after Reset (
RS), the Full-Flag (FF) will
go LOW after 512/1,024/2,048/4,096/8,192/16,384 writes to the IDT72V01/
72V02/72V03/72V04/72V05/72V06.
EMPTY FLAG (
EF)
The Empty Flag (
EF)willgoLOW,inhibitingfurtherreadoperations,when
the read pointer is equal to the write pointer, indicating that the device is empty.
EXPANSION OUT/HALF-FULL FLAG (
XO/HF)
This is a dual-purpose output. In the single device mode, when Expansion
In (
XI) is grounded, this output acts as an indication of a half-full memory.
After half of the memory is filled and at the falling edge of the next write
operation, the Half-Full Flag (
HF) will be set LOW and will remain set until the
difference between the write pointer and read pointer is less than or equal to
one half of the total memory of the device. The Half-Full Flag (
HF)isthenreset
by using rising edge of the read operation.
IntheDepthExpansionMode,ExpansionIn(
XI)isconnectedtoExpansion
Out (
XO)ofthepreviousdevice.Thisoutputactsasasignaltothenextdevice
in the Daisy Chain by providing a pulse to the next device when the previous
device reaches the last location of memory.
DATA OUTPUTS (Q0 – Q8)
Data outputs for 9-bit wide data. This data is in a high impedance condition
whenever Read (
R) is in a HIGH state.
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| 72V01L25JG | 制造商:Integrated Device Technology Inc 功能描述:FIFO ASYNC DUAL DEPTH/WIDTH UNI-DIR 512X9 32PLCC - Rail/Tube |
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| 72V01L25JI | 功能描述:先進(jìn)先出 512x9 3.3V ASYNC 先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
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