參數(shù)資料
型號： 71V3557SA75BGI8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： SRAM
英文描述： 128K X 36 ZBT SRAM, 7.5 ns, PBGA119
封裝： 14 X 22 MM, PLASTIC, BGA-119
文件頁數(shù)： 9/28頁
文件大?。?/td> 511K
代理商： 71V3557SA75BGI8
6.42
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
17
Timing Waveform of Read Cycle (1,2,3,4)
NOTES:
1.
Q
(A
1)
represents
the
first
output
from
the
external
address
A
1.
Q
(A
2)
represents
the
first
output
from
the
external
address
A
2;
Q
(A
2+1
)represents
the
next
output
data
in
the
burst
sequence
of
the
base
address
A
2,
etc.
where
address
bits
A
0and
A
1are
advancing
for
the
four
word
burst
in
the
sequence
defined
by
the
state
of
the
LBO
input.
2.
CE
2timing
transitions
are
identical
but
inverted
to
the
CE
1and
CE
2
signals.
For
example,
when
CE
1and
CE
2are
LOW
on
this
waveform,
CE
2is
HIGH.
3.
Burst
ends
when
new
address
and
control
are
loaded
into
the
SRAM
by
sampling
ADV/
LD
LOW.
4.
R/
W
is
don't
care
when
the
SRAM
is
bursting
(ADV/
LD
sampled
HIGH).
The
nature
of
the
burst
access
(Read
or
Write)
is
fixed
by
the
state
of
the
R/
W
signal
when
new
address
and
control
are
loaded
into
the
SRAM.
(C
E
N
hi
g
h
,
e
lim
inates
c
u
rr
ent
L-
H
cl
o
ck
edge
)
Q
(A
2+
1
)
tC
D
R
ea
d
tC
LZ
tC
H
Z
tC
D
tC
D
C
Q
(A
2+
2
)
Q
(A
1
)
Q
(A
2
)
Q
(A
2+
3
)
Q
(A
2+
3
)
Q
(A
2
)
B
ur
s
t
R
ea
d
R
ead
D
A
T
A
O
U
T
(B
ur
s
t
W
ra
p
s
a
rou
nd
to
in
it
ia
l
s
ta
te
)
tC
D
C
tH
A
D
V
52
82
drw
06
R
/W
C
LK
A
D
V
/LD
A
D
R
E
S
C
E
1
,
C
E
2
(2
)
B
W
1
-
B
W
4
O
E
tH
E
tS
E
A
1
A
2
tC
H
tC
L
tC
Y
C
tS
A
D
V
tH
W
tS
W
tH
A
tS
A
tH
C
tS
C
E
N
.
,
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