參數(shù)資料
型號： 71M6542G-IGT/F
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 模擬信號調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP100
封裝： LEAD FREE, LQFP-100
文件頁數(shù)： 31/165頁
文件大?。?/td> 2208K
代理商： 71M6542G-IGT/F
126
2008–2011 Teridian Semiconductor Corporation
v1.1
The parameters EQU[2:0] (I/O RAM 0x2106[7:5]), CE_E (I/O RAM 0x2106[0]), and SUM_SAMPS[12:0] are
essential to the function of the CE are stored in I/O RAM (see 5.2 I/O RAM Map – Alphabetical Order for
details).
5.3.4
Environment
Before starting the CE using the CE_E bit (I/O RAM 0x2106[0]), the MPU has to establish the proper
environment for the CE by implementing the following steps:
Locate the CE code in Flash memory using CE_LCTN[5:0] (I/O RAM 0x2109[5:0])
Load the CE data into RAM
Establish the equation to be applied in EQU[2:0] (I/O RAM 0x2106[7:5])
Establish the number of samples per accumulation period in SUM_SAMPS[12:0] (I/O RAM 0x2107[4:0],
0x2108[7:0])
Establish the number of cycles per ADC multiplexer frame (MUX_DIV[3:0] (I/O RAM 0x2100[7:4]))
Apply proper values to MUXn_SEL, as well as proper selections for DIFFn_E (I/O RAM 0x210C[5:4])
and RMT_E (I/O RAM 0x2709[3]) in order to configure the analog inputs
Initialize any MPU interrupts, such as CE_BUSY, XFER_BUSY, or the power failure detection interrupt
VMAX = 600 V, IMAX = 707 A, and kH = 1 Wh/pulse are assumed as default settings
When different CE codes are used, a different set of environment parameters need to be established.
The exact values for these parameters are listed in the Application Notes and other documentation which
accompanies the CE code.
Operating CE codes with environment parameters deviating from the values specified by Teridian
leads to unpredictable results. See Table 1 and Table 2.
Typically, there are thirteen 32768 Hz cycles per ADC multiplexer frame (see 2.2.2 Input Multiplexer).
This means that the product of the number of cycles per slot and the number of conversions per frame
must be 12 (plus one settling cycle per frame, see Figure 6 and Figure 7). The default configuration is
FIR_LEN[1:0] = 01, I/O RAM 0x210C[2:1], (three cycles per conversion) and MUX_DIV[3:0] = 3 (3
conversions per multiplexer cycle).
Sample configurations can be copied from Demo Code provided by Teridian with the Demo Kits.
5.3.5
CE Calculations
Referring to Table 78, The MPU selects the desired equation by writing the EQU[2:0] (I/O RAM
0x2106[7:5]).
Table 78: CE EQU Equations and Element Input Mapping
EQU
Watt & VAR Formula
(WSUM/VARSUM)
Inputs Used for Energy/Current Calculation
W0SUM/
VAR0SUM
W1SUM/
VAR1SUM
I0SQ
SUM
I1SQ
SUM
0
VA IA – 1 element, 2W 1
φ
VA*IA
VA*IB
IA
–
1
VA*(IA-IB)/2 – 1 element, 3W 1
φ
VA*(IA-IB)/2
–
IA-IB
IB
2
VA*IA + VB*IB – 2 element, 3W 3
φ Delta
VA*IA
VB*IB
IA
IB
Note:
71M6542F only.
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