參數(shù)資料
型號： 71M6541G-IGTR/F
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 模擬信號調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP64
封裝： LEAD FREE, LQFP-64
文件頁數(shù)： 96/165頁
文件大小： 2208K
代理商： 71M6541G-IGTR/F
36
2008–2011 Teridian Semiconductor Corporation
v1.1
Table 15: Port Registers (SEGDIO0-15)
SFR
Name
SFR
Address
D7
D6
D5
D4
D3
D2
D1
D0
P0
0x80
DIO_DIR[3:0]
DIO[3:0]
P1
0x90
DIO_DIR[7:4]
DIO[7:4]
P2
0xA0
DIO_DIR[11:8]
DIO[11:8]
P3
0xB0
DIO_DIR[15:12]
DIO[15:11]
Ports P0-P3 on the chip are bi-directional and control SEGDIO0-15. Each port consists of a Latch (SFR
P0 to P3), an output driver and an input buffer, therefore the MPU can output or read data through any of
these ports. Even if a DIO pin is configured as an output, the state of the pin can still be read by the
MPU, for example when counting pulses issued via DIO pins that are under CE control.
At power-up SEGDIO0-15 are configured as inputs. It is necessary to write PORT_E = 1 (I/O RAM
0x270C[5]) to enable SEGDIO0-15. The default PORT_E = 0 blocks any momentary output
transient pulses that would otherwise occur when SEGDIO0-15 are reset on power-up.
Clock Stretching (CKCON)
The three low order bits of the CKCON[2:0] (SFR 0x8E) register define the stretch memory cycles that
are used for MOVX instructions when accessing external peripherals. The practical value of this register
for the 71M6541D/F and 71M6542F is to guarantee access to XRAM between CE, MPU, and SPI. The
default setting of CKCON[2:0] (001) should not be changed.
Table 16 shows how the signals of the External Memory Interface change when stretch values are set
from 0 to 7. The widths of the signals are counted in MPU clock cycles. The post-reset state of the
CKCON[2:0] (001), which is shown in bold in the table, performs the MOVX instructions with a stretch
value equal to 1.
Table 16: Stretch Memory Cycle Width
CKCON[2:0]
Stretch
Value
Read Signal Width
Write Signal Width
memaddr
memrd
memaddr
memwr
000
0
1
2
1
001
1
2
3
1
010
2
3
4
2
011
3
4
5
3
100
4
5
6
4
101
5
6
7
5
110
6
7
8
6
111
7
8
9
7
2.4.4
Instruction Set
All instructions of the generic 8051 microcontroller are supported. A complete list of the instruction set
and of the associated op-codes is contained in the 71M654X Software User’s Guide (SUG).
2.4.5
UARTs
The 71M6541D/F and 71M6542F include a UART (UART0) that can be programmed to communicate
with a variety of AMR modules and other external devices. A second UART (UART1) is connected to the
optical port, as described in 2.5.7 UART and Optical Interface.
The UARTs are dedicated 2-wire serial interfaces, which can communicate with an external host processor
at up to 38,400 bits/s (with MPU clock = 1.2288 MHz). The operation of the RX and TX UART0 pins is as
follows:
相關(guān)PDF資料
PDF描述
71M6541F-IGTR/F SPECIALTY ANALOG CIRCUIT, PQFP64
71M6541D-IGTR/F SPECIALTY ANALOG CIRCUIT, PQFP64
71M6542F-IGTR/F SPECIALTY ANALOG CIRCUIT, PQFP100
71M6541D-IGT/F SPECIALTY ANALOG CIRCUIT, PQFP64
71M6542G-IGT/F SPECIALTY ANALOG CIRCUIT, PQFP100
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