參數資料
型號： 71M6541F-IGTR/F
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 模擬信號調理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP64
封裝： LEAD FREE, LQFP-64
文件頁數： 3/165頁
文件大?。?/td> 2208K
代理商： 71M6541F-IGTR/F
100
2008–2011 Teridian Semiconductor Corporation
v1.1
GAIN_ADJ2 provides compensation for the remotely connected IB shunt current sensor and compensates
for the 71M6x01 VREF. The designer may optionally add compensation for the shunt connected to the
71M6x01 into the PPMC and PPMC2 coefficients for this channel.
Table 73: GAIN_ADJn Compensation Channels
Gain Adjustment Output
CE RAM Address
71M6541D/F
71M6542F
GAIN_ADJ0
0x40
VA
VA, VB
GAIN_ADJ1
0x41
IA
GAIN_ADJ2
0x42
IB
In the demonstration code, temperature compensation behavior is determined by the values stored in the
PPMC and PPMC2 coefficients, which are setup by the MPU demo code at initialization time from values
that are previously stored in EEPROM.
To disable temperature compensation in the demonstration code, PPMC and PPMC2 are both set to zero
for each of the three GAIN_ADJn channels. To enable temperature compensation, the PPMC and PPMC2
coefficients are set with values that match the expected temperature variation of the corresponding
channel.
For VREF compensation, both the linear coefficient PPMC and the quadratic coefficient PPMC2, are
determined for the 71M654x as described in 4.7.2 Temperature Coefficients for the 71M654x. For
information on determining the PPMC and PPMC2 coefficients for the 71M6x01 VREF, refer to the
71M6xxx Data Sheet.
The compensation for the external error sources is accomplished by summing the PPMC value
associated with VREF with the PPMC value associated with the external error source to obtain the final
PPMC value for the sensor channel. Similarly, the PPMC2 value associated with VREF is summed with
the PPMC2 value associated with the external error source.
To determine the contribution of the current shunt sensor to the PPMC and PPMC2 coefficients, the
designer must either know the temperature coefficients of the shunt from its data sheet or obtain it by
laboratory measurement. The designer must consider component variation across mass production to
ensure that the product will meet its accuracy requirement across production.
4.8
Connecting I
2C EEPROMs
I
2C EEPROMs or other I2C compatible devices should be connected to the DIO pins SEGDIO2 and
SEGDIO3, as shown in Figure 39.
Pull-up resistors of roughly 10 k
to V3P3D (to ensure operation in BRN mode) should be used for both
SDCK and SDATA signals. The DIO_EEX[1:0] (I/O RAM 0x2456[7:6]) field in I/O RAM must be set to 01
in order to convert the DIO pins SEGDIO2 and SEGDIO3 to I
2C pins SDCK and SDATA.
Figure 39: I
2C EEPROM Connection
SEGDIO2/SDCK
EEPROM
SDCK
SDATA
V3P3D
10 k
Ω
10 k
Ω
71M654x
SEGDIO3/SDATA
相關PDF資料
PDF描述
71M6541D-IGTR/F SPECIALTY ANALOG CIRCUIT, PQFP64
71M6542F-IGTR/F SPECIALTY ANALOG CIRCUIT, PQFP100
71M6541D-IGT/F SPECIALTY ANALOG CIRCUIT, PQFP64
71M6542G-IGT/F SPECIALTY ANALOG CIRCUIT, PQFP100
71M6541G-IGT/F SPECIALTY ANALOG CIRCUIT, PQFP64
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