參數(shù)資料
型號： 71M6541F-IGT/F
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 模擬信號調理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP64
封裝： LEAD FREE, LQFP-64
文件頁數(shù)： 33/165頁
文件大?。?/td> 2208K
代理商： 71M6541F-IGT/F
128
2008–2011 Teridian Semiconductor Corporation
v1.1
status flags for the preceding CE code pass (CE_BUSY interrupt). The significance of the bits in
CESTATUS is shown in Table 81.
Table 81: CESTATUS (CE RAM 0x80) Bit Definitions
CESTATUS
bit
Name
Description
31:4
Not Used
These unused bits are always zero.
3
F0
F0 is a square wave at the exact fundamental input frequency.
2
Not Used
This unused bit is always zero.
1
SAG_B
Normally zero. Becomes one when VB remains below SAG_THR for
SAG_CNT samples. Does not return to zero until VB rises above
SAG_THR.
0
SAG_A
Normally zero. Becomes one when VA remains below SAG_THR for
SAG_CNT samples. Does not return to zero until VA rises above
SAG_THR.
The CE is initialized by the MPU using CECONFIG (Table 82). This register contains in packed form
SAG_CNT, FREQSEL[1:0], EXT_PULSE, PULSE_SLOW and PULSE_FAST. The CECONFIG bit definitions are
given in Table 83.
Table 82: CECONFIG Register
CE
Address
Name
Data
Description
0x20
CECONFIG
0x0030DB00
1
0x00B0DB00
2
See description of the CECONFIG bits in
1.
Default for CE41A01 (71M6541D/F or CE41A04 (71M6542F) CE code for use with local
sensors.
2.
Default for CE41B016201 and CE41B016601 codes that support the 71M6x01 remote
sensors.
Table 83: CECONFIG (CE RAM 0x20) Bit Definitions
CECONFIG
bit
Name
Default
Description
23
Reserved
0
When this bit is set, control of temperature compensation is
enabled for the 71M6x01 Isolated Sensor Interface.
22
EXT_TEMP
0
When 1, the MPU controls temperature compensation via the
GAIN_ADJn registers (CE RAM 0x40-0x42), when 0, the CE is in
control.
21
EDGE_INT
1
When 1, XPULSE produces a pulse for each zero-crossing of
the mains phase selected by FREQSEL[1:0] , which can be used
to interrupt the MPU.
20
SAG_INT
1
When 1, activates YPULSE output when a sag condition is
detected.
19:8
SAG_CNT
252
(0xFC)
The number of consecutive voltage samples below SAG_THR
(CE RAM 0x24) before a sag alarm is declared. The default value
is equivalent to 100 ms.
7:6
FREQSEL[1:0]
0
FREQSEL[1:0] selects the phase to be used for the frequency
monitor, sag detection, and for the zero crossing counter
(MAINEDGE_X, CE RAM 0x83).
FREQ SEL[1:0]
Phase Selected
0
A
0
1
B*
1
X
Not allowed
*71M6542F only
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