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參數(shù)資料
| 型號(hào)： | 71M6533-IGTR/F |
| 廠商： | TERIDIAN SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP100 |
| 封裝： | LEAD FREE, LQFP-100 |
| 文件頁數(shù)： | 32/124頁 |
| 文件大?。?/td> | 2008K |
| 代理商： | 71M6533-IGTR/F |
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FDS_6533_6534_004
71M6533/71M6534 Data Sheet
v1.1
2007-2009 TERIDIAN Semiconductor Corporation
15
Table 4 shows the CE addresses in XRAM allocated to analog inputs from the AFE.
Table 4: XRAM Locations for ADC Results
Address (HEX)
Name
Description
0x00
IA
Phase A current
0x01
VA
Phase A voltage
0x02
IB
Phase B current
0x03
VB
Phase B voltage
0x04
IC
Phase C current
0x05
VC
Phase C voltage
0x06
ID
Neutral current
0x07 – 0x09
–
Not used
0x0A
TEMP
Temperature
0x0B
VBAT
Battery Voltage
The CE is aided by support hardware to facilitate implementation of equations, pulse counters, and ac-
cumulators. This hardware is controlled through I/O RAM locations EQU (equation assist), DIO_PV and
DIO_PW (pulse count assist), and PRE_SAMPS and SUM_CYCLES (accumulation assist).
PRE_SAMPS and SUM_CYCLES support a dual-level accumulation scheme where the first accumulator
accumulates results from PRE_SAMPS samples and the second accumulator accumulates up to
SUM_CYCLES of the first accumulator results. The integration time for each energy output is
PRE_SAMPS * SUM_CYCLES/2520.6 (with MUX_DIV = 6). CE hardware issues the XFER_BUSY interrupt
when the accumulation is complete.
1.2.10 Meter Equations
The 71M6533 and 71M6534 provide hardware assistance to the CE in order to support various meter
equations. This assistance is controlled through I/O RAM location EQU (equation assist). The Compute
Engine (CE) firmware for industrial configurations can implement the equations listed in Table 5. EQU
specifies the equation to be used based on the meter configuration and on the number of phases used for
metering.
Table 5: Inputs Selected in Regular and Alternate Multiplexer Cycles
EQU Description
Wh and VARh formula
Mux
Sequence
ALT Mux Se-
quence
Element 0
Element 1
Element
2
0
1 element, 2 W, 1
φ with
neutral current sense
VA IA
VA IB
N/A
Sequence is
programmable
with
SLOTn_SEL
Sequence is
programmable
with
SLOTn_ALTSEL
1
1 element, 3 W, 1
φ
VA(IA-IB)/2
N/A
2
2 element, 3 W, 3
φ Delta
VA IA
VB IB
N/A
3
2 element, 4 W, 3
φ Delta
VA(IA-IB)/2
VC IC
N/A
4
2 element, 4 W, 3
φ Wye
VA(IA-IB)/2
VB(IC-IB)/2
N/A
5
3 element, 4 W, 3
φ Wye
VA IA
VB IB
VC IC
1.2.11 Real-Time Monitor
The CE contains a Real-Time Monitor (RTM), which can be programmed to monitor four selectable XRAM
locations at full sample rate. The four monitored locations are serially output to the TMUXOUT pin via the
digital output multiplexer at the beginning of each CE code pass. The RTM can be enabled and disabled
with RTM_E. The RTM output is clocked by CKTEST. Each RTM word is clocked out in 35 cycles and con-
tains a leading flag bit. See Figure 19 for the RTM output format. RTM is low when not in use.
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