- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄68811 > 71M6532D-IGT/F (MAXIM INTEGRATED PRODUCTS INC) 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP100 PDF資料下載
參數(shù)資料
| 型號(hào)： | 71M6532D-IGT/F |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP100 |
| 封裝： | LEAD FREE, LQFP-100 |
| 文件頁(yè)數(shù)： | 100/120頁(yè) |
| 文件大?。?/td> | 2477K |
| 代理商： | 71M6532D-IGT/F |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)當(dāng)前第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)
Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
80
2005-2010 TERIDIAN Semiconductor Corporation
v1.3
Name
Location
Reset
Wake
Dir
Description
FLSH_ERASE
[7:0]
SFR 94[7:0]
0
W
Flash Erase Initiate. (Default = 0x00). FLSH_ERASE is used to initiate either the Flash
Mass Erase cycle or the Flash Page Erase cycle. Specific patterns are expected for
FLSH_ERASE in order to initiate the appropriate Erase cycle.
0x55 = Initiate Flash Page Erase cycle. Must be proceeded by a write to
FLSH_PGADR[5:0] @ SFR 0xB7.
0xAA = Initiate Flash Mass Erase cycle. Must be proceeded by a write to
FLSH_MEEN @ SFR 0xB2 and the debug (CC) port must be enabled.
Any other pattern written to FLSH_ERASE will have no effect. The erase cycle is not
completed until 0x00 is written to FLSH_ERASE.
FLSH_MEEN
SFR B2[1]
0
W
Mass Erase Enable.
0 = Mass Erase disabled (default).
1 = Mass Erase enabled.
Must be re-written for each new Mass Erase cycle.
FLSH_PGADR
[5:0]
SFR B7 [7:2]
0
W
Flash Page Erase Address. (Default = 0x00)
FLSH_PGADR[5:0] with FL_BANK[2:0], sets the Flash Page Address (page 0 through
127) that will be erased during the Page Erase cycle.
Must be re-written for each new Page Erase cycle.
FLSH_PWE
SFR B2[0]
0
R/W
Program Write Enable. This bit must be cleared by the MPU after each byte write op-
eration. Write operations to this bit are inhibited when interrupts are enabled.
0 = MOVX commands refer to XRAM Space, normal operation (default).
1 = MOVX @DPTR,A moves A to Program Space (Flash) @ DPTR.
GP0
…
GP7
20C0
…
20C7
0
…
0
NV
…
NV
R/W
Non-volatile general-purpose registers powered by the RTC supply. These registers
maintain their value in all power modes, but will be cleared on reset. The values of
GP0…GP7 will be undefined if VBAT drops below the minimum value.
IE_FWCOL0
IE_FWCOL1
SFR E8[2]
SFR E8[3]
0
R/W
Interrupt flags for Firmware Collision Interrupt. See the Flash Memory section for
details.
IE_PB
SFR E8[4]
0
–
R/W
PB flag. Indicates that a rising edge occurred on PB. Firmware must write a zero to
this bit to clear it. The bit is also cleared when the MPU requests SLEEP or LCD
mode. On bootup, the MPU can read this bit to determine if the part was woken with
the PB (DIO0[0]).
IE_PLLRISE
SFR E8[6]
0
R/W
Indicates that the MPU was woken or interrupted (INT4) by system power becoming
available, or more precisely, by PLL_OK rising. The firmware must write a zero to this
bit to clear it.
IE_PLLFALL
SFR E8[7]
0
R/W
Indicates that the MPU has entered BROWNOUT mode because system power has
become unavailable (INT4), or more precisely, because PLL_OK fell. This bit will not
be set if the part wakes into BROWNOUT mode because of PB or the WAKE timer.
The firmware must write a zero to this bit to clear it.
IEN_SPI
20B0[4]
0
–
R/W
SPI interrupt enable.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 71M6531D-IMR/F | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC68 |
| 71M6532F-IGTR/F | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP100 |
| 71M6532D-IGT/F | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP100 |
| 71M6531D-IM/F | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC68 |
| 71M6532F-IGTR/F | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 71M6532D-IGTR/F | 功能描述:計(jì)量片上系統(tǒng) - SoC Residential Energy Meter IC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 處理器系列:71M6511 類型:Metering SoC 最大時(shí)鐘頻率:70 Hz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:7 KB 接口類型:UART 可編程輸入/輸出端數(shù)量:12 片上 ADC: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:LQFP-64 封裝:Reel |
| 71M6532D-IGTR/F1 | 功能描述:計(jì)量片上系統(tǒng) - SoC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 處理器系列:71M6511 類型:Metering SoC 最大時(shí)鐘頻率:70 Hz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:7 KB 接口類型:UART 可編程輸入/輸出端數(shù)量:12 片上 ADC: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:LQFP-64 封裝:Reel |
| 71M6532F | 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:Energy Meter IC |
| 71M6532F-IGT/F | 功能描述:計(jì)量片上系統(tǒng) - SoC Residential Energy Meter IC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 處理器系列:71M6511 類型:Metering SoC 最大時(shí)鐘頻率:70 Hz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:7 KB 接口類型:UART 可編程輸入/輸出端數(shù)量:12 片上 ADC: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:LQFP-64 封裝:Reel |
| 71M6532F-IGT/F1 | 功能描述:計(jì)量片上系統(tǒng) - SoC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 處理器系列:71M6511 類型:Metering SoC 最大時(shí)鐘頻率:70 Hz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:7 KB 接口類型:UART 可編程輸入/輸出端數(shù)量:12 片上 ADC: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:LQFP-64 封裝:Reel |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。