參數(shù)資料
型號(hào)： 71M6531F-IMR/F
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 電源管理
英文描述： 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC68
封裝： LEAD FREE, QFN-68
文件頁(yè)數(shù)： 38/120頁(yè)
文件大?。?/td> 2477K
代理商： 71M6531F-IMR/F
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Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
24
2005-2010 TERIDIAN Semiconductor Corporation
v1.3
Table 12: Port Registers
Register
SFR
Address
R/W
Description
P0
0x80
R/W
Register for port 0 read and write operations.
DIR0
0xA2
R/W
Data direction register for port 0. Setting a bit to 1 indicates that the
corresponding pin is an output.
P1
0x90
R/W
Register for port 1 read and write operations.
DIR1
0x91
R/W
Data direction register for port 1.
P2
0xA0
R/W
Register for port 2 read and write operations.
DIR2
0xA1
R/W
Data direction register for port 2.
All DIO ports on the chip are bi-directional. Each of them consists of a Latch (SFR P0 to P2), an output
driver and an input buffer, therefore the MPU can output or read data through any of these ports. Even if
a DIO pin is configured as an output, the state of the pin can still be read by the MPU, for example when
counting pulses issued via DIO pins that are under CE control.
The technique of reading the status of or generating interrupts based on DIO pins configured as
outputs can be used to implement pulse counting.
Clock Stretching (CKCON[2:0], SFR 0x8E)
The CKCON[2:0] field defines the stretch memory cycles that could be used for MOVX instructions when
accessing slow external peripherals. The practical value of this register for the 71M653x is to guarantee
access to XRAM between CE, MPU, and SPI. The default setting of CKCON[2:0] (001) should not be
changed.Table 13 shows how the signals of the External Memory Interface change when stretch values
are set from 0 to 7. The widths of the signals are counted in MPU clock cycles. The post-reset state of
the CKCON[2:0] field (001), which is shown in bold in the table, performs the MOVX instructions with a
stretch value equal to 1.
Table 13: Stretch Memory Cycle Width
CKCON[2:0]
Stretch
Value
Read signal width
Write signal width
memaddr
memrd
memaddr
memwr
000
0
1
2
1
001
1
2
3
1
010
2
3
4
2
011
3
4
5
3
100
4
5
6
4
101
5
6
7
5
110
6
7
8
6
111
7
8
9
7
1.4.4
Special Function Registers (SFRs) Specific to the 71M6531D/F and 71M6532D/F
Table 14 shows the location and description of the SFRs specific to the 71M6531D/F and 71M6532D/F.
Table 14: 71M6531D/F and 71M6532D/F Specific SFRs
Register
(Alternate Name)
SFR
Address
Bit Field
Name
R/W
Description
EEDATA
0x9E
R/W
I
2C EEPROM interface data register.
EECTRL
0x9F
R/W
I
2C EEPROM interface control register. See
description of the command and status bits
available for EECTRL.
相關(guān)PDF資料
PDF描述
71M6532D-IGT/F 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP100
71M6531D-IMR/F 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC68
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