參數(shù)資料
型號： 71M6531F-IMR/F
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 電源管理
英文描述： 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC68
封裝： LEAD FREE, QFN-68
文件頁數(shù)： 107/120頁
文件大小： 2477K
代理商： 71M6531F-IMR/F
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
v1.3
2005-2010 TERIDIAN Semiconductor Corporation
87
Name
Location
Reset
Wake
Dir
Description
TRIMSEL[3:0]
20FD[3:0]
0
R/W
Selects the trim fuse to be read with the TRIM register:
TRIMSEL[3:0]
Trim Fuse
Purpose
1
TRIMT[7:0]
Trim for the magnitude of VREF
VERSION[7:0]
2006
20C8
–
R
The device version index. This word may be read by the firmware to determine the
silicon version.
VERSION[7:0]
Silicon Version
0001 0101
A05
VREF_CAL
2004[7]
0
R/W
Brings VREF to the VREF pad. This feature is disabled when VREF_DIS =1.
VREF_DIS
2004[3]
0
R/W
Disables the internal voltage reference.
WAKE_ARM
20A9[7]
0
–
W
Arm the autowake timer. Writing a 1 to this bit arms the autowake timer and presets it
with the values presently in WAKE_PRD and WAKE_RES. The autowake timer is reset and
disarmed whenever the IC is in MISSION or BROWNOUT mode. The timer must be
armed at least three RTC cycles before the SLEEP or LCD-ONLY mode is commanded.
WAKE_PRD
20A9[2:0]
001
–
R/W
Sleep time. Time = WAKE_PRD[2:0]*WAKE_RES. Default = 001. Maximum value is 7.
WAKE_RES
20A9[3]
0
–
R/W
Resolution of WAKE timer: 1 = 1 minute, 0 = 2.5 seconds.
WD_NROVF_
FLAG
20B1[0]
–
0
R/W
This flag is set approximately 1 ms before the watchdog timer overflows. It is cleared
by writing a 0 or on the falling edge of WAKE.
WD_RST
SFR F8[7]
0
W
WD timer bit. This bit must
WD_OVF
be accessed with byte operations. Operations possible for
this bit are: Write 0xFF: Resets the WDT.
2002[2]
0
R/W
The WD overflow status bit. This bit is set when the WD timer overflows. It is powered
by the nonvolatile supply and at bootup will indicate if the part is recovering from a WD
overflow or a power fault. This bit should be cleared by the MPU on bootup. It is also
automatically cleared when RESET is high.
WE
201F[7:0]
–
W
An 8-bit value has to be written to this address prior to accessing the RTC registers.
WRPROT_BT
SFR B2[5]
0
When set, this bit protects flash addresses from 0 to BOOT_SIZE*1024 from flash page
erase.
WRPROT_CE
SFR B2[4]
0
When set, this bit protects flash addresses from CE_LCTN*1024 to the end of memory
from flash page erase.
相關(guān)PDF資料
PDF描述
71M6532D-IGT/F 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP100
71M6531D-IMR/F 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC68
71M6532F-IGTR/F 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP100
71M6532D-IGT/F 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP100
71M6531D-IM/F 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC68
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71M6531-IMTR 制造商:Maxim Integrated Products 功能描述:- Tape and Reel
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