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| 型號(hào)： | 71M6531D-IM/F |
| 廠商： | TERIDIAN SEMICONDUCTOR CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC68 |
| 封裝： | LEAD FREE, QFN-68 |
| 文件頁(yè)數(shù)： | 13/120頁(yè) |
| 文件大?。?/td> | 2477K |
| 代理商： | 71M6531D-IM/F |
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FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
v1.3
2005-2010 TERIDIAN Semiconductor Corporation
11
1.2.2
Input Multiplexer
The input multiplexer supports up to four input signals that are applied to pins IA (IAP/IAN), VA, IB
(IBP/IBN), and VB of the device. Additionally, using the alternate multiplexer selection, it has the ability to
select temperature and the battery voltage. The multiplexer can be operated in two modes:
During a normal multiplexer cycle, the signals from the IA (IAP/IAN), IB (IBP/IBN), VA and VB pins
are selected.
During the alternate multiplexer cycle, the temperature signal (TEMP) and the battery monitor are
selected, along with some of the voltage and/or current signal sources shown in Table 1. To prevent
unnecessary drainage on the battery, the battery monitor is only active when enabled with the BME
bit (0x2020[6]) in the I/O RAM.
The alternate multiplexer cycles are usually performed infrequently (every second or so) by the MPU. In
order to prevent disruption of the voltage tracking PLL and voltage allpass networks, VA is not replaced in
the ALT selections. Table 1 details the regular and alternative multiplexer sequences. The computation
engine (CE) fills in missing samples due to an ALT multiplexer sequence.
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles
Time
Slot
Regular Slot
Alternate Slot
Register
Typical Selections
Register
Typical Selections
RAM
Address
Signal for
ADC
RAM
Address
Signal for
ADC
0
SLOT0_SEL[3:0]
0
IA
SLOT0_ALTSEL[3:0]
A
TEMP
1
SLOT1_SEL[3:0]
1
VB
SLOT1_ALTSEL[3:0]
1
VB
2
SLOT2_SEL[3:0]
2
IB
SLOT2_ALTSEL[3:0]
B
VBAT
3
SLOT3_SEL[3:0]
3
VA
SLOT3_ALTSEL[3:0]
3
VA
–
SLOT4_SEL[3:0]
–
SLOT4_ALTSEL[3:0]
–
SLOT5_SEL[3:0]
–
SLOT5_ALTSEL[3:0]
–
SLOT6_SEL[3:0]
–
SLOT6_ALTSEL[3:0]
–
SLOT7_SEL[3:0]
–
SLOT7_ALTSEL[3:0]
–
SLOT8_SEL[3:0]
–
SLOT8_ALTSEL[3:0]
–
SLOT9_SEL[3:0]
–
SLOT9_ALTSEL[3:0]
–
The sequence of sampled channels is fully programmable using I/O RAM registers. SLOTn_SEL[3:0]
selects the input for the nth state in a standard multiplexer frame, while SLOTn_ALTSEL[3:0] selects the
input for the nth state in an alternate multiplexer frame. The states shown in Table 1 are examples for
possible multiplexer state sequences.
In a typical application, IA (IAN/IAP) and IB (IBN/IBP) are connected to current transformers that sense
the current on each phase of the line voltage. VA and VB are typically connected to voltage sensors
through resistor dividers.
The multiplexer control circuit (MUX_CTRL signal) controls multiplexer advance, FIR initiation and VREF
chopping. Additionally, MUX_CTRL launches each pass through the CE program. Conceptually,
MUX_CTRL is clocked by CK32, the 32768 Hz clock from the PLL block. The behavior of MUX_CTRL is
governed by MUX_ALT, EQU[2:0], CHOP_E[1:0] and MUX_DIV[3:0].
The MUX_ALT bit requests an alternative multiplexer frame. The bit may be asserted on any MPU cycle
and may be subsequently de-asserted on any cycle including the next one. A rising edge on MUX_ALT
will cause MUX_CTRL to wait until the next multiplexer frame and implement a single alternate multiplexer
frame.
Another control input to the MUX is MUX_DIV[3:0]. These four bits can request from 1 to 10 multiplexer
states per frame. The multiplexer always starts at the beginning of its list and proceeds until the number
of states defined by MUX_DIV[3:0] have been converted.
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