參數(shù)資料
型號(hào): 71M6521FE-IMR/F
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 模擬信號(hào)調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, QCC68
封裝: LEAD FREE, LQFN-68
文件頁數(shù): 9/103頁
文件大小: 1691K
代理商: 71M6521FE-IMR/F
71M6521DE/71M6521FE
Energy Meter IC
DATA SHEET
OCTOBER 2010
v1.1
2005-2010 Teridian Semiconductor Corporation
Page: 13 of 103
A Maxim Integrated Products Brand
19-5370; 10/10
Battery Monitor
The battery voltage is measured by the ADC during alternative multiplexer frames if the BME (Battery Measure Enable) bit in
the I/O RAM is set. While BME is set, an on-chip 45k
load resistor is applied to the battery, and a scaled fraction of the
battery voltage is applied to the ADC input. After each alternative MUX frame, the result of the ADC conversion is available at
CE DRAM address 07. BME is ignored and assumed zero when system power is not available (V1 < VBIAS). See the Battery
Monitor section of the Electrical Specifications for details regarding the ADC LSB size and the conversion accuracy.
Functional Description
The AFE functions as a data acquisition system, controlled by the MPU. The main signals (IA, VA, IB, VB) are sampled and
the ADC counts obtained are stored in CE DRAM where they can be accessed by the CE and, if necessary, by the MPU.
Alternate multiplexer cycles are initiated less frequently by the MPU to gather access to the slow temperature and battery
signals.
IA
VA
MUX
VREF
4.9MHz
VBIAS
CROSS
CK32
VREF
VREF_DIS
MUX
CTRL
MUX_DIV
CHOP_E
EQU
IB
MUX
MUX_ALT
V3P3A
FIR_LEN
FIR
VB
VBIAS
VREF_CAL
Σ ADC
CONVERTER
+
-
VREF
ADC_E
TEMP
VBAT
FIR_DONE
FIR_START
Figure 3: AFE Block Diagram
Digital Computation Engine (CE)
The CE, a dedicated 32-bit signal processor, performs the precision computations necessary to accurately measure energy.
The CE calculations and processes include:
Multiplication of each current sample with its associated voltage sample to obtain the energy per sample (when
multiplied with the constant sample time).
Frequency-insensitive delay cancellation on all six channels (to compensate for the delay between samples caused
by the multiplexing scheme).
90
° phase shifter (for VAR calculations).
Pulse generation.
Monitoring of the input signal frequency (for frequency and phase information).
Monitoring of the input signal amplitude (for sag detection).
Scaling of the processed samples based on calibration coefficients.
The CE program resides in flash memory. Common access to flash memory by CE and MPU is controlled by a memory share
circuit. Each CE instruction word is two bytes long. Allocated flash space for the CE program cannot exceed 1024 words
(2KB). The CE program counter begins a pass through the CE code each time multiplexer state 0 begins. The code pass ends
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