參數(shù)資料
型號(hào): 7140LA35CB
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 1K X 8 DUAL-PORT SRAM, 35 ns, CDIP48
封裝: SIDE BRAZED, DIP-48
文件頁(yè)數(shù): 7/19頁(yè)
文件大?。?/td> 153K
代理商: 7140LA35CB
15
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
tINS
ADDR'A'
INT'B'
INTERRUPT ADDRESS
tWC
tAS
R/
W'A'
tWR
2689 drw 16
(3)
(2)
(4)
INT
Set:
Timing Waveform of Interrupt Mode(1)
NOTES:.
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. See Interrupt Truth Table II.
3. Timing depends on which enable signal (
CE or R/W) is asserted last.
4. Timing depends on which enable signal (
CE or R/W) is de-asserted first.
INT
Clear:
AC Electrical characteristics Over the
Operating Temperature and Supply Voltage Range(1)
NOTES:
1.
'X' in part numbers indicates power rating (SA or LA).
7130X55
7140X55
Com'l, Ind
& Military
7130X100
7140X100
Com'l, Ind
& Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
____
0
____
ns
tWR
Write Recovery Time
0
____
0
____
ns
tINS
Interrupt Set Time
____
45
____
60
ns
tINR
Interrupt Reset Time
____
45
____
60
ns
2689 tbl 12b
tRC
INTERRUPT CLEAR ADDRESS
ADDR'B'
OE'B'
tINR
INT'A'
2689 drw 17
tAS
(3)
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