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參數(shù)資料
| 型號(hào)： | 7140LA35CB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 1K X 8 DUAL-PORT SRAM, 35 ns, CDIP48 |
| 封裝： | SIDE BRAZED, DIP-48 |
| 文件頁數(shù)： | 13/19頁 |
| 文件大小： | 153K |
| 代理商： | 7140LA35CB |
3
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
INDEX
IDT7130/40TF or PF
PP64-1 & PN64-1(4)
64-Pin STQFP
64-Pin TQFP
Top View(5)
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
46
45
44
43
42
41
40
39
38
37
36
35
34
47
48
33
I/O6R
N/C
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
I/O7R
OER
N/C
I/O2L
A0L
OEL
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
N/C
2689 drw 05
1
7
1
8
1
9
2
0
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
1
4
9
5
0
5
1
5
2
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
4
5
3
6
4
N
/C
N
/C
N
/C
N
/C
N
/C
N
/C
G
N
D
N
/C
N
/C
G
N
D
N
/C
R
/W
R
C
E
R
V
C
V
C
B
U
S
Y
L
IN
T
L
I/
O
3
L
I/
O
4
L
I/
O
5
L
I/
O
6
L
I/
O
7
L
I/
O
0
R
I/
O
1
R
I/
O
2
R
I/
O
3
R
I/
O
4
R
I/
O
5
R
/W
L
C
E
L
B
U
S
Y
R
IN
T
R
,
01/08/02
IDT7130/40J
J52-1(4)
52-Pin PLCC
Top View(5)
INDEX
N
/C
G
N
D
N
/C
N
/C
C
E
R
C
E
L
O
E
L
A
0
L
OER
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
N/C
I/O7R
46
45
44
43
42
41
40
39
38
37
36
35
34
I/O3L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
8
9
10
11
12
13
14
15
16
17
18
19
20
47
48
49
50
51
52
1
2
3
4
5
6
7
33
32
31
30
29
28
27
26
25
24
23
22
21
2689 drw 04
IN
T
L
B
U
S
Y
L
R
/W
L
R
/W
R
B
U
S
Y
R
IN
T
R
I/
O
6
R
V
C
I/
O
5
R
I/
O
4
R
I/
O
3
R
I/
O
2
R
I/
O
1
R
I/
O
0
R
I/
O
7
L
I/
O
6
L
I/
O
5
L
I/
O
4
L
,
01/08/02
Pin Configurations(1,2,3) (con't.)
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J52-1 package body is approximately .75 in x .75 in x .17 in.
PP64-1 package body is approximately 10 mm x 10 mm x 1.4mm.
PN64-1 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
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