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參數(shù)資料
| 型號(hào)： | 70V25S15PFG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 8K X 16 DUAL-PORT SRAM, 15 ns, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 6/25頁 |
| 文件大小： | 211K |
| 代理商： | 70V25S15PFG |
6.42
IDT70V35/34S/L
(IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
14
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
NOTES:
1. R/
W or CE or UB & LB must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW
UB or LB and a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of
CE or R/W (or SEM or R/W) going HIGH to the end-of-write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the
CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition the outputs remain in the HIGH-impedance state.
6. Timing depends on which enable signal is asserted last,
CE, R/W, or UB or LB.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with Output Test Load
(Figure 2).
8. If
OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If
OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as
the specified tWP.
9. To access SRAM,
CE = VIL, UB or LB = VIL, and SEM = VIH. To access Semaphore, CE = VIH or UB and LB = VIH, and SEM = VIL. tEW must be met for either condition.
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)
R/
W
tWC
tHZ
tAW
tWR
tAS
tWP
DATAOUT
(2)
tWZ
tDW
tDH
tOW
OE
ADDRESS
DATAIN
(6)
(4)
(7)
CE or SEM
5624 drw 09
(9)
CE or SEM
(9)
(7)
(3)
5624 drw 10
tWC
tAS
tWR
tDW
tDH
ADDRESS
DATAIN
R/
W
tAW
tEW
UB or LB
(3)
(2)
(6)
CE or SEM
(9)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 70V25S20J | 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC DUAL 3.3V 128KBIT 8KX16 20NS 84PLCC - Rail/Tube |
| 70V25S20J8 | 功能描述:IC SRAM 128KBIT 20NS 84PLCC 制造商:idt, integrated device technology inc 系列:- 包裝:帶卷（TR） 零件狀態(tài):有效 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，異步 存儲(chǔ)容量:128K（8K x 16） 速度:20ns 接口:并聯(lián) 電壓 - 電源:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C（TA） 封裝/外殼:84-LCC（J 形引線） 供應(yīng)商器件封裝:84-PLCC（29.21x29.21） 標(biāo)準(zhǔn)包裝:200 |
| 70V25S20PF | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 8Kx16, 3.3V DUAL- PORT RAM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| 70V25S20PF8 | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 8Kx16, 3.3V DUAL- PORT RAM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| 70V25S25G | 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC DUAL 3.3V 128KBIT 8KX16 25NS 84PIN PGA - Trays |
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