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參數(shù)資料
| 型號(hào)： | 70V05S55G |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 8K X 8 DUAL-PORT SRAM, 55 ns, CPGA68 |
| 封裝： | 1.180 X 1.180 INCH, 0.160 INCH HEIGHT, CERAMIC, PGA-68 |
| 文件頁數(shù)： | 13/22頁 |
| 文件大?。?/td> | 159K |
| 代理商： | 70V05S55G |
6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
20
completelyindependentofeachother.Thismeansthattheactivityonthe
left port in no way slows the access time of the right port. Both ports are
identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom,
oraccessed,atthesametimewiththeonlypossibleconflictarisingfrom
the simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphorelocation. Semaphoresareprotectedagainstsuchambiguous
situationsandmaybeusedbythesystemprogramtoavoidanyconflicts
in the non-semaphore portion of the Dual-Port SRAM. These devices
haveanautomaticpower-downfeaturecontrolledbyCE,theDual-Port
SRAMenable,andSEM,thesemaphoreenable.TheCEandSEMpins
controlon-chippowerdowncircuitrythatpermitstherespectiveporttogo
intostandbymodewhennotselected. Thisistheconditionwhichisshown
in Truth Table II where CE and SEM are both HIGH.
SystemswhichcanbestusetheIDT70V05containmultipleprocessors
or controllers and are typically very high-speed systems which are
softwarecontrolledorsoftwareintensive.Thesesystemscanbenefitfrom
a performance increase offered by the IDT70V05's hardware sema-
phores, which provide a lockout mechanism without requiring complex
programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in
varying configurations. The IDT70V05 does not use its semaphore
flags to control any resources through hardware, thus allowing the
system designer total flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred
in either processor. This can prove to be a major advantage in very
high-speed systems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are indepen-
dent of the Dual-Port SRAM. These latches can be used to pass a flag,
or token, from one port to the other to indicate that a shared resource
is in use. The semaphores provide a hardware assist for a use
assignment method called “Token Passing Allocation.” In this method,
the state of a semaphore latch is used as a token indicating that shared
resource is in use. If the left processor wants to use this resource, it
requests the token by setting the latch. This processor then verifies its
success in setting the latch by reading it. If it was successful, it
proceeds to assume control over the shared resource. If it was not
successful in setting the latch, it determines that the right side
processor has set the latch first, has the token and is using the shared
resource. The left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore to
perform another task and occasionally attempt again to gain control of
the token via the set and test sequence. Once the right side has
relinquished the token, the left side should succeed in gaining control.
Thesemaphoreflagsareactivelow.Atokenisrequestedbywriting
a zero into a semaphore latch and is released when the same side
writes a one to that latch.
The eight semaphore flags reside within the IDT70V05 in a
separate memory space from the Dual-Port SRAM. This address
space is accessed by placing a LOW input on the SEM pin (which acts
as a chip select for the semaphore flags) and using the other control
pins (Address, OE, and R/W) as they would be used in accessing a
standardStaticRAM.Eachoftheflagshasauniqueaddresswhichcan
beaccessedbyeithersidethroughaddresspinsA0–A2.Whenaccessing
the semaphores, none of the other address pins has any effect.
Whenwritingtoasemaphore,onlydatapinD0isused.IfaLOWlevel
iswrittenintoanunusedsemaphorelocation,thatflagwillbesettoazero
on that side and a one on the other side (see Truth Table V). That
semaphorecannowonlybemodifiedbythesideshowingthezero.When
aoneiswrittenintothesamelocationfromthesameside,theflagwillbe
settoaoneforbothsides(unlessasemaphorerequestfromtheotherside
ispending)andthencanbewrittentobybothsides. Thefactthattheside
whichisabletowriteazerointoasemaphoresubsequentlylocksoutwrites
fromtheothersideiswhatmakessemaphoreflagsusefulininterprocessor
communications.(Athoroughdiscussionontheuseofthisfeaturefollows
shortly.) A zero written into the same location from the other side will be
storedinthesemaphorerequestlatchforthatsideuntilthesemaphoreis
freed by the first side.
Whenasemaphoreflagisread,itsvalueisspreadintoalldatabitsso
thataflagthatisaonereadsasaoneinalldatabitsandaflagcontaining
azeroreadsasallzeros.Thereadvalueislatchedintooneside’soutput
registerwhenthatside'ssemaphoreselect(SEM)andoutputenable(OE)
signalsgoactive.Thisservestodisallowthesemaphorefromchanging
stateinthemiddleofareadcycleduetoawritecyclefromtheotherside.
Becauseofthislatch,arepeatedreadofasemaphoreinatestloopmust
cause either signal (SEM or OE) to go inactive or the output will never
change.
A sequence WRITE/READ must be used by the semaphore in
order to guarantee that no system level contention will occur. A
processor requests access to shared resources by attempting to write
a zero into a semaphore location. If the semaphore is already in use,
the semaphore request latch will contain a zero, yet the semaphore
flag will appear as one, a fact which the processor will verify by the
subsequent read (see Truth Table V). As an example, assume a
processor writes a zero to the left port at a free semaphore location. On
a subsequent read, the processor will verify that it has written success-
fully to that location and will assume control over the resource in
question. Meanwhile, if a processor on the right side attempts to write
a zero to the same semaphore flag it will fail, as will be verified by the
fact that a one will be read from that semaphore on the right side during
subsequent read. Had a sequence of READ/WRITE been used
instead, system contention problems could have occurred during the
gap between the read and write cycles.
It is important to note that a failed semaphore request must be
followed by either repeated reads or by writing a one into the same
location. The reason for this is easily understood by looking at the
simple logic diagram of the semaphore flag in Figure 4. Two sema-
phore request latches feed into a semaphore flag. Whichever latch is
first to present a zero to the semaphore flag will force its side of the
semaphore flag LOW and the other side HIGH. This condition will
continue until a one is written to the same semaphore request latch.
Should the other side’s semaphore request latch have been written to
a zero in the meantime, the semaphore flag will flip over to the other
side as soon as a one is written into the first side’s request latch. The
second side’s flag will now stay LOW until its semaphore request latch
is written to a one. From this it is easy to understand that, if a
semaphoreisrequestedandtheprocessorwhichrequesteditnolonger
needs the resource, the entire system can hang up until a one is written
intothatsemaphorerequestlatch.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| 70V05S55J | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 8K x 8 3.3v Dual- Port Ram RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| 70V05S55J8 | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 8K x 8 3.3v Dual- Port Ram RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| 70V05S55PF | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 8K x 8 3.3v Dual- Port Ram RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| 70V05S55PF8 | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 8K x 8 3.3v Dual- Port Ram RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| 70V05S55PFI | 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC DUAL 3.3V 64KBIT 8KX8 55NS 64TQFP - Bulk |
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