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參數(shù)資料
| 型號(hào)： | 70V05L20J |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | SRAM |
| 英文描述： | 8K X 8 DUAL-PORT SRAM, 20 ns, PQCC68 |
| 封裝： | 0.950 X 0.950 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-68 |
| 文件頁(yè)數(shù)： | 3/22頁(yè) |
| 文件大?。?/td> | 159K |
| 代理商： | 70V05L20J |
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6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
11
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,3,5,8)
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE, or R/W.
7. Timing depends on which enable signal is de-asserted first, CE, or R/W.
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the
bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9. To access RAM, CE = VIL and SEM = VIN. To access Semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,3,5,8)
2941 drw 09
tWC
tAS
tWR
tDW
tDH
ADDRESS
DATAIN
CE or SEM
R/
W
tAW
tEW
(3)
(2)
(6)
(9)
R/
W
tWC
tHZ
tAW
tWR
tAS
tWP
DATAOUT
(2)
tWZ
tDW
tDH
tOW
OE
ADDRESS
DATAIN
CE
(6)
(4)
(3)
2941 drw 08
(7)
or
SEM
(9)
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| 70V05L20J8 | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 8K x 8 3.3v Dual- Port Ram RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| 70V05L20JI | 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC DUAL 3.3V 64KBIT 8KX8 20NS 68PLCC - Rail/Tube 制造商:Integrated Device Technology Inc 功能描述:8K x 8 3.3v Dual- Port Ram |
| 70V05L20JI8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Async Dual 3.3V 64K-Bit 8K x 8 20ns 68-Pin PLCC T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC DUAL 3.3V 64KBIT 8KX8 20NS 68PLCC - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:8K x 8 3.3v Dual- Port Ram |
| 70V05L20PF | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 8K x 8 3.3v Dual- Port Ram RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| 70V05L20PF8 | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 8K x 8 3.3v Dual- Port Ram RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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