參數(shù)資料
型號(hào): 70V05L20J
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 8K X 8 DUAL-PORT SRAM, 20 ns, PQCC68
封裝: 0.950 X 0.950 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-68
文件頁數(shù): 22/22頁
文件大?。?/td> 159K
代理商: 70V05L20J
6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
9
Waveform of Read Cycles(5)
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no
relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
tRC
R/
W
CE
ADDR
tAA
OE
2941 drw 07
(4)
tACE
(4)
tAOE
(4)
(1)
tLZ
tOH
(2)
tHZ
(3,4)
tBDD
DATAOUT
BUSYOUT
VALID DATA
(4)
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