- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄157981 > 7052S25G (INTEGRATED DEVICE TECHNOLOGY INC) 2K X 8 FOUR-PORT SRAM, 25 ns, CPGA108 PDF資料下載
參數(shù)資料
| 型號： | 7052S25G |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 2K X 8 FOUR-PORT SRAM, 25 ns, CPGA108 |
| 封裝： | 1.210 X 1.210 INCH, 0.160 INCH HEIGHT, PGA-108 |
| 文件頁數(shù)： | 2/11頁 |
| 文件大?。?/td> | 123K |
| 代理商： | 7052S25G |
6.42
IDT7052S/L
High-Speed 2K x 8 FourPort Static RAM
Military, Industrial and Commercial Temperature Ranges
10
Timing Waveform of Write with Port-to-Port Read(1,2,3)
Functional Description
The IDT7052 provides four ports with separate control, address, and
I/O pins that permit independent access for reads or writes to any location
in memory. These devices have an automatic power down feature
controlled by
CE. The CE controls on-chip power down circuitry that
permitstherespectiveporttogointostandbymodewhennotselected(
CE
= VIH). When a port is enabled, access to the entire memory array is
permitted. Each port has its own Output Enable control (
OE). In the read
mode, the port’s
OE turns on the output drivers when set LOW. READ/
WRITE conditions are illustrated in the table below.
Timing Waveform of Write with BUSY Input
NOTES:
1.
BUSY is asserted on Port "B" blocking R/W"B" until BUSY"B" goes HIGH.
Truth Table I – Read/Write Control(3)
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don’t Care, "Z "= High Impedance
2. If
BUSY = VIL, write is blocked.
3. For valid write operation, no more than one port can write to the same address
location at the same time.
NOTES:
1. Assume
BUSY input = VIH and CE = VIL for the writing port.
2.
OE = VIL for the reading ports.
3. All timing is the same for left and right ports. Port "A" may be either of the four ports and Port "B" is any other port.
2674 drw 11
ADDR"A"
tWC
DATA"B"
MATCH
tWP
R/
W"A"
DATAIN"A"
ADDR"B"
tDH
VALID
MATCH
VALID
tDDD
tWDD
tDW
2674 drw 12
R/
W"A"
BUSY"B"
tWP
tWH
tWB
R/
W"B"
(1)
,
Any Port
(1)
R/
W
CE
OE
D0-7
Function
X
H
X
Z
Port Deselected: Power-Down
XH
X
Z
CEP1=CEP2=CEP3=CEP4=VIH
Power Down Mode ISB or ISB1
LL
X
DATAIN
Data on port written into memory
(2)
HL
L
DATAOUT
Data in memory output on port
X
H
Z
Outputs Disabled
2674 tbl 11
相關PDF資料 |
PDF描述 |
|---|---|
| 7054-50 | 20 A, BARRIER STRIP TERMINAL BLOCK, 1 ROW, 1 DECK |
| 7064-50B5TH | 64 CONTACT(S), MALE, RIGHT ANGLE TWO PART EURO CONNECTOR, SOLDER |
| 707-1014 | WIRE TERMINAL |
| 707-1778 | WIRE TERMINAL |
| 707-1780 | WIRE TERMINAL |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 7052S25PQF | 功能描述:靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| 7052S30GB | 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC QUAD 5V 16KBIT 2KX8 30NS 108PIN PGA - Bulk |
| 7052S35G | 功能描述:IC SRAM 16KBIT 35NS 108PGA 制造商:idt, integrated device technology inc 系列:- 包裝:托盤 零件狀態(tài):有效 格式 - 存儲器:RAM 存儲器類型:SRAM - 四端口，異步 存儲容量:16K（2K x 8） 速度:35ns 接口:并聯(lián) 電壓 - 電源:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C（TA） 封裝/外殼:108-BPGA 供應商器件封裝:108-PGA（30.48x30.48） 標準包裝:3 |
| 7052S35GB | 功能描述:靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| 7052S35PQF | 功能描述:IC SRAM 16KBIT 35NS 132QFP 制造商:idt, integrated device technology inc 系列:- 包裝:托盤 零件狀態(tài):過期 格式 - 存儲器:RAM 存儲器類型:SRAM - 四端口，異步 存儲容量:16K（2K x 8） 速度:35ns 接口:并聯(lián) 電壓 - 電源:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C（TA） 封裝/外殼:132-BQFP 緩沖式 供應商器件封裝:132-PQFP（24.13x24.13） 標準包裝:18 |
發(fā)布緊急采購，3分鐘左右您將得到回復。