參數(shù)資料
型號(hào)： 7016S35PFGB
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： SRAM
英文描述： 16K X 9 DUAL-PORT SRAM, 35 ns, PQFP80
封裝： 14 X 14 MM, 1.40 MM HEIGHT, GREEN, TQFP-80
文件頁(yè)數(shù)： 4/20頁(yè)
文件大?。?/td> 164K
代理商： 7016S35PFGB
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
12
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6)
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveformof Write with Port-to-Port Read and
BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on Port "B" during contention on Port "A".
5. To ensure that a write cycle is completed on Port "B" after contention on Port "A".
6. 'X' in part numbers indicates power rating (S or L).
7016X12
Com'l Only
7016X15
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S = VIH)
tBAA
BUSY Access Time from Address Match
____
12
____
15
ns
tBDA
BUSY Disable Time from Address Not Matched
____
12
____
15
ns
tBAC
BUSY Access Time from Chip Enable Low
____
12
____
15
ns
tBDC
BUSY Disab le Time from Chip Enable High
____
12
____
15
ns
tAPS
Arbitration Priority Set-up Time(2)
5
____
5
____
ns
tBDD
BUSY Disable to Valid Data(3)
____
15
____
18
ns
tWH
Write Hold After
BUSY(5)
11
____
13
____
ns
BUSY INPUT TIMING (M/S = VIL)
tWB
BUSY Input to Write(4)
0
____
0
____
ns
tWH
Write Hold After
BUSY(5)
11
____
13
____
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
____
25
____
30
ns
tDDD
Write Data Valid to Read Data Delay(1)
____
20
____
25
ns
3190 tbl 14a
7016X20
Com'l, Ind
& Military
7016X25
Com'l &
Military
7016X35
Com'l &
Military
Symbol
Parameter
Min.
Max.Min.Max.Min.
Max.
Unit
BUSY TIMING (M/S = VIH)
tBAA
BUSY Access Time from Address Match
____
20
____
20
____
20
ns
tBDA
BUSY Disable Time from Address Not Matched
____
20
____
20
____
20
ns
tBAC
BUSY Access Time from Chip Enable Low
____
20
____
20
____
20
ns
tBDC
BUSY Disab le Time from Chip Enable High
____
17
____
17
____
20
ns
tAPS
Arbitration Priority Set-up Time(2)
5
____
5
____
5
____
ns
tBDD
BUSY Disable to Valid Data(3)
____
30
____
30
____
35
ns
tWH
Write Hold After
BUSY(5)
15
____
17
____
25
____
ns
BUSY INPUT TIMING (M/S = VIL)
tWB
BUSY Input to Write(4)
0
____
0
____
0
____
ns
tWH
Write Hold After
BUSY(5)
15
____
17
____
25
____
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
____
45
____
50
____
60
ns
tDDD
Write Data Valid to Read Data Delay(1)
____
30
____
35
____
45
ns
3190 tbl 14b
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