Inter-IC Bus
IIC Register Descriptions
68HC(9)12DG128 Rev 1.0
MOTOROLA
Inter-IC Bus
261
11-iicbus
Read and write anytime
IBEN — IIC Bus Enable
This bit controls the software reset of the entire IIC module.
0 = The module is reset and disabled. This is the power-on reset
situation. When low the IIC system is held in reset but registers
can still be accessed.
1 = The IIC system is enabled. This bit must be set before any other
IBCR bits have any effect.
If the IIC module is enabled in the middle of a byte transfer the
interface behaves as follows: slave mode ignores the current transfer
on the bus and starts operating whenever a subsequent start
condition is detected. Master mode will not be aware that the bus is
busy, hence if a start cycle is initiated then the current bus cycle may
become corrupt. This would ultimately result in either the current bus
master or the IIC module losing arbitration, after which bus operation
would return to normal.
IBIE — IIC Bus Interrupt Enable
0 = Interrupts from the IIC module are disabled. Note that this does
not clear any currently pending interrupt condition.
1 = Interrupts from the IIC module are enabled. An IIC interrupt
occurs provided the IBIF bit in the status register is also set.
1B
128
17
3B
2048
257
1C
144
25
3C
2304
385
1D
160
25
3D
2560
385
1E
192
33
3E
3072
513
1F
240
33
3F
3840
513
Table 37 IIC Divider and SDA Hold values
IBC5-0
(hex)
SCL Divider
(clocks)
SDA Hold
(clocks)
IBC5-0
(hex)
SCL Divider
(clocks)
SDA Hold
(clocks)
IBCR
— IIC Bus Control Register
$00E2
Bit 7
IBEN
0
6
5
4
3
2
1
0
0
Bit 0
IBSWAI
0
IBIE
0
MS/SL
0
Tx/Rx
0
TXAK
0
RSTA
0
RESET: