Clock Functions
68HC912DG128 Rev 1.0
162
Clock Functions
MOTOROLA
Figure 22 Clock Chain for MSCAN, SPI, ATD0, ATD1 and BDM
Computer Operating Properly (COP)
The COP or watchdog timer is an added check that a program is running
and sequencing properly. When the COP is being used, software is
responsible for keeping a free running watchdog timer from timing out. If
the watchdog timer times out it is an indication that the software is no
longer being executed in the intended sequence; thus a system reset is
initiated. Three control bits allow selection of seven COP time-out
periods. When COP is enabled, sometime during the selected period the
program must write $55 and $AA (in this order) to the COPRST register.
If the program fails to do this the part will reset. If any value other than
$55 or $AA is written, the part is reset.
In addition, windowed COP operation can be selected. In this mode,
writes to the COPRST register must occur in the last 25% of the selected
period. A premature write will also reset the part.
PCLK
REGISTER: SP0BR
: SPR2, SPR1, SPR0
0:0:0
SPI
BIT RATE
5-BIT MODULUS
COUNTER (PR0-PR4)
TO ATD0
and ATD1
ECLK
BKGD
PIN
LOGIC
BDM BIT CLOCK:
Receive: Detect falling edge,
count 12 E clocks, Sample input
Transmt 1: Detect falling edge,
count 6 E clocks while output is
high impedance, Drive out 1 E
cycle pulse high, high imped-
ance output again
Transmt 0: Detect falling edge,
Drive out low, count 9 E clocks,
Drive out 1 E cycle pulse high,
high impedance output
SYNCHRONIZER
BKGD IN
BKGD OUT
BKGD DIRECTION
÷
2
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
÷
2
÷
2
÷
2
÷
2
÷
2
÷
2
÷
2
÷
2
TO MSCAN
CLKSW
EXTALi
SYSCLK
24-clock