Analog-To-Digital Converter (ATD)
68HC(9)12DG128 Rev 1.0
282
Analog-To-Digital Converter (ATD)
MOTOROLA
The ATD status registers contain the flags indicating the completion of
ATD conversions.
Normally, it is read-only. In special mode, the SCF bit and the CCF bits
may also be written.
SCF — Sequence Complete Flag
This bit is set at the end of the conversion sequence when in the
single conversion sequence mode (SCAN = 0 in ATDxCTL5) and is
set at the end of the first conversion sequence when in the continuous
conversion mode (SCAN = 1 in ATDxCTL5). When AFFC = 0, SCF is
cleared when a write is performed to ATDxCTL5 to initiate a new
conversion sequence. When AFFC = 1, SCF is cleared after the first
result register is read.
CC[2:0] — Conversion Counter for Current Sequence of Four or Eight
Conversions
This 3-bit value reflects the contents of the conversion counter pointer
in a four or eight count sequence. This value also reflects which result
register will be written next, indicating which channel is currently
being converted.
CCF[7:0] — Conversion Complete Flags
Each of these bits are associated with an individual ATD result
register. For each register, this bit is set at the end of conversion for
the associated ATD channel and remains set until that ATD result
register is read. It is cleared at that time if AFFC bit is set, regardless
ATD0STAT0/ATD1STAT0
— ATD Status Register
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Bit 7
6
5
4
3
2
1
Bit 0
SCF
0
0
0
0
CC2
CC1
CC0
RESET:
0
0
0
0
0
0
0
0
ATD0STAT1/ATD1STAT1
— ATD Status Register
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Bit 7
CCF7
0
6
5
4
3
2
1
Bit 0
CCF0
0
CCF6
0
CCF5
0
CCF4
0
CCF3
0
CCF2
0
CCF1
0
RESET:
10-atd