參數資料
| 型號： | 668-0003-C |
| 廠商： | Rabbit Semiconductor |
| 文件頁數： | 36/228頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPU RABBIT2000 30MHZ 100PQFP |
| 標準包裝： | 100 |
| 系列： | Rabbit 2000 |
| 處理器類型： | Rabbit 2000 8-位 |
| 速度： | 30MHz |
| 電壓： | 2.7V，3V，3.3V，5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-BQFP |
| 供應商設備封裝： | 100-PQFP（14x20） |
| 包裝： | 托盤 |
| 其它名稱： | 316-1004 668-0003 |
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124
Rabbit 2000 Microprocessor User’s Manual
12.3 Transmit Serial Data Timing
On transmit, if the interrupts are enabled, an interrupt is requested when the transmit regis-
ter becomes empty and, in addition, an interrupt occurs when the shift register and trans-
mit register both become empty, that is, when the transmitter becomes idle. When the
transmit data register contains data and the shift register finishes sending data, the data bits
are clocked from the transmit register to the shift register, and the shift register is never
idle. The interrupt request is cleared either by writing to the data register or by writing to
the status register (which does not affect the status register). The data register normally is
clocked into the shift register each time the shift register finishes sending data, leaving the
data register empty. This causes an interrupt request. The interrupt routine normally
answers the interrupt before the shift register runs dry (9 to 11 baud clocks, depending on
the mode of operation). The interrupt routine stores the next data item in the data register,
clearing the interrupt request and supplying the next data bits to be sent. When all the
characters have been sent, the interrupt service routine answers the interrupt once the data
register becomes empty. Since it has no more data, it clears the interrupt request by storing
to the status register. At this point the routine should check if the shift register is empty;
normally it won’t be. If it is, because the interrupt was answered late, the interrupt routine
should do any final cleanup and store to the status register again in case the shift register
became empty after the pending interrupt is cleared. Normally, though, the interrupt ser-
vice routine will return and there will be a final interrupt to give the routine a chance to
disable the output buffers, as in the case for RS-485 transmission.
12.4 Receive Serial Data Timing
When the receiver is ready to receive data, a falling edge indicates that a start bit must be
detected. The falling edge is detected as a different Rx input between two different clocks,
the clock being 16x the baud rate. Once the start bit has been detected, data bits are sam-
pled at the middle of each data bit and are shifted into the receive shift register. After 7 or
8 data bits have been received, the next bit will be either a 9th (8th) address bit, or a stop
bit will be sampled. If the Rx line is low, it is an address bit and the address bit received bit
in the status register will be enabled. If an address bit is detected, the receiver will attempt
to sample the stop bit. If the line is high when sampled, it is a stop bit and a new scan for a
new start bit will begin after the sample point. At the same time, the data bits are trans-
ferred into the receive data register and an interrupt, if enabled, is requested.
On receive, an interrupt is requested when the receiver data register has data. This happens
when data bits are transferred from the receive shift register to the data register. This also
sets bit 7 of the status register. The interrupt request and bit 7 are cleared when the data
register is read.
An interrupt is requested if bit 7 is high. The interrupt is requested on the edge of the trans-
mitter data register becoming empty or the transmitter shift register becoming empty. The
transmitter interrupt is cleared by writing to the status register or to the data register.
On receive, the scan for the next start bit starts immediately after the stop bit is detected.
The stop bit is normally detected at a sample clock that nominally occurs in the center of
the stop bit. If there is a 9th (8th) address bit, the stop bit follows that bit.
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