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| 型號： | 62LV12816 |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 128K x 16 CMOS STATIC RAM |
| 中文描述： | 128K的× 16的CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 83K |
| 代理商： | 62LV12816 |
IS62LV12816L
6
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION
SR002-0C
08/20/98
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range)
-70
-100
-120
Symbol
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWB
t
PWE
t
SD
t
HD
t
HZWE
(3)
t
LZWE
(3)
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Write Cycle Time
70
—
100
—
120
—
ns
CE
to Write End
65
—
80
—
100
—
ns
Address Setup Time to Write End
65
—
80
—
100
—
ns
Address Hold from Write End
0
—
0
—
0
—
ns
Address Setup Time
0
—
0
—
0
—
ns
LB
,
UB
Valid to End of Write
60
—
80
—
100
—
ns
WE
Pulse Width
60
—
80
—
100
—
ns
Data Setup to Write End
30
—
40
—
50
—
ns
Data Hold from Write End
0
—
0
—
0
—
ns
WE
LOW to High-Z Output
—
30
—
40
—
50
ns
WE
HIGH to Low-Z Output
5
—
5
—
5
—
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to
2.2V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of
CE
LOW and
UB
or
LB
, and
WE
LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to
the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured
±
500 mV from steady-state voltage. Not 100% tested.
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE
t
LZCE
t
HZOE
HIGH-Z
DATA VALID
t
HZB
ADDRESS
OE
CE
LB, UB
D
OUT
t
HZCE
t
BA
t
LZB
AC WAVEFORMS
READ CYCLE NO. 2
(1,3)
Notes:
1.
WE
is HIGH for a Read Cycle.
2. The device is continuously selected.
OE
,
CE
,
UB
, or
LB
= V
IL
.
3. Address is valid prior to or coincident with
CE
LOW transition.
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