參數(shù)資料
型號: 62LV12816
廠商: Integrated Silicon Solution, Inc.
英文描述: 128K x 16 CMOS STATIC RAM
中文描述: 128K的× 16的CMOS靜態(tài)RAM
文件頁數(shù): 1/9頁
文件大?。?/td> 83K
代理商: 62LV12816
IS62LV12816L
IS62LV12816L
128K x 16 CMOS STATIC RAM
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION
SR002-0C
08/20/98
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FEATURES
High-speed access time: 70, 100, and 120 ns
CMOS low power operation
– 120 mW (typical) operating
– 6
μ
W (typical) CMOS standby
TTL compatible interface levels
Single 3V
±
10% V
CC
power supply
Fully static operation: no clock or refresh
required
Three state outputs
Data control for upper and lower bytes
Industrial temperature available
Available in the 44-pin TSOP (Type II) and
48-pin mini BGA
DESCRIPTION
The
ISSI
IS62LV12816L is a high-speed, 2,097,152-bit static
RAM organized as 131,072 words by 16 bits. It is fabricated
using
ISSI
's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design
techniques, yields high-performance and low power
consumption devices.
When
CE
is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down
with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs,
CE
and
OE
. The active LOW Write
Enable (
WE
) controls both writing and reading of the memory.
A data byte allows Upper Byte (
UB
) and Lower Byte (
LB
)
access.
The IS62LV12816L is packaged in the JEDEC standard
44-pin TSOP (Type II) and 48-pin mini BGA.
FUNCTIONAL BLOCK DIAGRAM
ADVANCE INFORMATION
AUGUST 1998
The specification contains ADVANCE INFORMATION. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible
product. We assume no responsibility for any errors which may appear in this publication. Copyright 1998, Integrated Silicon Solution, Inc.
A0-A16
CE
OE
WE
UB
LB
128K x 16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
ISSI
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