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參數(shù)資料
| 型號(hào)： | 6276 |
| 廠商： | Allegro MicroSystems, Inc. |
| 元件分類： | LED驅(qū)動(dòng)器 |
| 英文描述： | 16-BIT SERIAL-INPUT, CONSTANTCURRENT LATCHED LED DRIVER |
| 中文描述： | 16位串行輸入，CONSTANTCURRENT鎖存LED驅(qū)動(dòng) |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大?。?/td> | 154K |
| 代理商： | 6276 |
6276
16-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
10
The load current per bit (I
O
) is set by the external resistor
(R
EXT
) as shown in the figure below.
300
500
700
1 k
2 k
CURRENT-CONTROL RESISTANCE, R
EXT
IN OHMS
100
0100
Dwg. GP-061
O
5 k
200
3 k
20
40
60
80
V
CE
= 0.7 V
Package Power Dissipation (P
D
).
The maximum
allowable package power dissipation is determined as
P
D
(max) = (150 - T
A
)/R
θ
JA
.
The actual package power dissipation is
P
D
(act) = dc(V
CE
I
O
16) + (V
DD
I
DD
).
When the load supply voltage is greater than 3 V to 5 V,
considering the package power dissipating limits of these
devices, or if P
D
(act) > P
D
(max), an external voltage
reducer (V
DROP
) should be used.
Load Supply Voltage (V
LED
).
These devices are
designed to operate with driver voltage drops (V
CE
) of
0.4 V to 0.7 V with LED forward voltages (V
F
) of 1.2 V to
4.0 V. If higher voltages are dropped across the driver,
package power dissipation will be increased significantly.
To minimize package power dissipation, it is recom-
mended to use the lowest possible load supply voltage or
to set any series dropping voltage (V
DROP
) as
V
DROP
= V
LED
- V
F
- V
CE
with V
DROP
= I
o
R
DROP
for a single driver, or a Zener
diode (V
Z
), or a series string of diodes (approximately
0.7 V per diode) for a group of drivers. If the available
voltage source will cause unacceptable dissipation and
series resistors or diode(s) are undesirable, a regulator
such as the Sanken Series SAI or Series SI can be used to
provide supply voltages as low as 3.3 V.
For reference, typical LED forward voltages are:
White
Blue
Green
Yellow
Amber
Red
Infrared
3.5 – 4.0 V
3.0 – 4.0 V
1.8 – 2.2 V
2.0 – 2.1 V
1.9 – 2.65 V
1.6 – 2.25 V
1.2 – 1.5 V
Pattern Layout.
This device has a common logic-
ground and power-ground terminal. If ground pattern
layout contains large common-mode resistance, and the
voltage between the system ground and the LATCH
ENABLE or CLOCK terminals exceeds 2.5 V (because of
switching noise), these devices may not operate correctly.
Dwg. EP-064
VLED
VDROP
VF
VCE
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