參數(shù)資料
型號: 5962R9675501TXX
廠商: INTERSIL CORP
元件分類: DAC
英文描述: PARALLEL, WORD INPUT LOADING, 12-BIT DAC, CDFP24
封裝: CERAMIC, DFP-24
文件頁數(shù): 6/6頁
文件大小: 108K
代理商: 5962R9675501TXX
6
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certication.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Die Characteristics
DIE DIMENSIONS:
(2718
m x 4547m x 483m ±25.4m)
107 x 179 x 19mils
±1mil
METALLIZATION:
Type: Al Si Cu
Thickness: 16.0k
±2k
SUBSTRATE POTENTIAL:
Tie substrate to reference ground
BACKSIDE FINISH:
Silicon
PASSIVATION:
Type: Silox (SiO2)
Thickness: 8k
±1k
WORST CASE CURRENT DENSITY:
< 2.0e5 A/cm2
TRANSISTOR COUNT:
200
PROCESS:
Bipolar, Dielectric Isolation
Metallization Mask Layout
HS-565ARH-T
VCC
(MSB)
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12
(LSB)
POWER
GND
20V
SPAN
10V
SPAN
IDAC
OUT
BIPOLAR
RIN
-VEE
VREF IN
VREF
GND
VREF OUT
3
HS-565ARH-T
相關(guān)PDF資料
PDF描述
5962R9675501TXC PARALLEL, WORD INPUT LOADING, 12-BIT DAC, CDFP24
5962R9675501TJC PARALLEL, WORD INPUT LOADING, 12-BIT DAC, CDIP24
5962R9675501V9X PARALLEL, WORD INPUT LOADING, 12-BIT DAC, UUC24
5962R9675501VXX PARALLEL, WORD INPUT LOADING, 0.35 us SETTLING TIME, 12-BIT DAC, CDFP24
5962R9675501VJX PARALLEL, WORD INPUT LOADING, 0.35 us SETTLING TIME, 12-BIT DAC, CDIP24
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