參數(shù)資料
型號: 5962R9675501TXX
廠商: INTERSIL CORP
元件分類: DAC
英文描述: PARALLEL, WORD INPUT LOADING, 12-BIT DAC, CDFP24
封裝: CERAMIC, DFP-24
文件頁數(shù): 3/6頁
文件大小: 108K
代理商: 5962R9675501TXX
3
Applying the HS-565ARH-T
OP AMP Selection
The HS-565ARH-T’s current output may be converted to
voltage using the standard connections shown in Figures 1
and 2. The choice of operational amplier should be
reviewed for each application, since a signicant trade-off
may be made between speed and accuracy. Remember
settling time for the DAC-amplier combination
is:
where tD, tA are settling times for the DAC and amplier.
No Trim Operation
The HS-565ARH-T will perform as specied without
calibration adjustments. To operate without calibration,
substitute 50
resistors for the 100 trimming
potentiometers: In Figure 1 replace R2 with 50
; also
remove the network on pin 8 and connect 50
to ground.
For bipolar operation in Figure 2, replace R3 and R4 with
50
resistors.
With these changes, performance is guaranteed as shown
under Specications, “External Adjustments”. Typical
unipolar zero will be
±0.50 LSB plus the op amp offset.
The feedback capacitor C must be selected to minimize
settling time.
t
D
()2
t
A
()2
+
FIGURE 1. UNIPOLAR VOLTAGE OUTPUT
FIGURE 2. BIPOLAR VOLTAGE OUTPUT
VO
-
+
R (SEE
TABLE 7)
DAC
OUT
9
10
11
20V SPAN
10V SPAN
2.5K
5K
C
9.95K
IO
24
13
MSB
LSB
. . . . .
CODE
INPUT
DAC
(4 x IREF
-VEE
PWR
GND
7
x CODE)
IREF
0.5mA
HS-565ARH-T
3K
3.5K
19.95
K
+
-
10V
3
4
VCC
+
-
6
5
REF
GND
REF
IN
REF OUT
R2
100
8
BIP.
OFF.
+15V
-15V
R1
50k
100k
100
VO
-
+
R (SEE
TABLE 7)
DAC
OUT
9
10
11
20V SPAN
10V SPAN
2.5K
5K
C
9.95K
IO
24
13
MSB
LSB
. . . . .
CODE
INPUT
DAC
(4 x IREF
-VEE
PWR
GND
7
x CODE)
IREF
0.5mA
HS-565ARH-T
3K
3.5K
19.95K
+
-
10V
3
4
VCC
+
-
6
5
REF
GND
REF
IN
REF OUT
R4
100
8
BIP.
OFF.
R3
100
HS-565ARH-T
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5962R9675501TXC PARALLEL, WORD INPUT LOADING, 12-BIT DAC, CDFP24
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