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參數(shù)資料
| 型號： | 5962R9566901VCA |
| 廠商： | INTERSIL CORP |
| 元件分類： | 取樣保持放大器 |
| 英文描述： | SAMPLE AND HOLD AMPLIFIER, CDIP14 |
| 封裝： | FRIT SEAL, CERDIP-14 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 135K |
| 代理商： | 5962R9566901VCA |
3
FIGURE 4. ACQUISITION TIME (tACQ TO 0.01% IS SHOWN, tACQ TO 0.1% IS DONE IN THE SAME MANNER)
FIGURE 5.
Test Circuits (Continued)
INCREMENT t2
BY 50ns
(50ns LONGER DELAY)
SEND SAMPLE
COMMAND
SET t2 TO 7s
INITIALLY
DIGITIZE V1
AT t1 (≈10s)
DIGITIZE V2
AT t2
DECREMENT
t2 BY 50ns
CALCULATE V1 - V2
IS
V ≥ 0.01%?
NO
YES
COURSE tACQ
MEASUREMENT LOOP
DECREMENT
t2 BY 50ns
DIGITIZE V1
AT t1 (≈10s)
DIGITIZE V2
AT t2
CALCULATE V1 - V2
IS
V ≥ 0.01%?
RECORD
tACQ
NO
YES
FINE tACQ
MEASUREMENT LOOP
NOTE: See Test Diagram, Timing Diagram
COMPUTER
CONTROLLER
V1 DIGITIZER
V2 DIGITIZER
V1
V2
t2
VARIABLE
DELAY
t2 DELAY
CONTROL
t1
≈10s
1000pF
2k
t1
-
+
-
+
S/H
CONTROL
HS-2420RH
+10V
0V
-10V
OR
50pF
DELAY
HS-2420RH
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