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參數(shù)資料
| 型號： | 5962R9566901VCA |
| 廠商： | INTERSIL CORP |
| 元件分類： | 取樣保持放大器 |
| 英文描述： | SAMPLE AND HOLD AMPLIFIER, CDIP14 |
| 封裝： | FRIT SEAL, CERDIP-14 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大小： | 135K |
| 代理商： | 5962R9566901VCA |
2
Test Circuits
FIGURE 1. TEST FIXTURE SCHEMATIC (SWITCH POSITIONS S1 - S8 DETERMINE CONFIGURATION)
NOTE: Compute Hold Mode Feedthrough Attenuation from the
Formula:
Where VOUT HOLD = Peak-Peak Value of Output Sinewave during
the Hold Mode.
FIGURE 2. HOLD MODE FEEDTHROUGH ATTENUATION
NOTE: GBWP is the Frequency of VINPUT at which:
FIGURE 3. GAIN BANDWIDTH PRODUCT
DUT
-
+
A
S/H
-VCC
+VCC
CH =
1000pF
50
2
21
1
S2
S1
2
1
S6
1
2
S7
1
2
50
VAC
AOUT
EOUT
50
1M
4
3
2
1
S8
3
2
S3
1
+VCC
GND
50pF
2k
1
S5
OPEN
3
2
S4
1
100k
VDC
10k
ILOAD
NULL
AMP
X1
X-1
BUFFER
100k
ALL RESISTORS =
±1%
ALL CAPACITORS =
±10%
+
-
+
-
CH =
VOUT
50pF
2k
+15V
-15V
1000pF
DUT
VIN
OUT
A0
EN
IN2
IN1
IN3
IN4
IN5
IN6
IN7
IN8
A2
A1
SINEWAVE
INPUT
SAMPLE/HOLD
CONTROL INPUT
+5V
+
-
FeedthroughAttenuation
20 log
V
OUT HOLD
V
IN HOLD
--------------------------------
=
CH =
VOUT
50pF
2k
+15V
-15V
1000pF
DUT
S/H
50
+
-
20 log
V
OUT
V
INPUT
---------------------
3dB
–
=
HS-2420RH
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