參數(shù)資料
型號(hào)： 5962R1023701QXC
元件分類： 多路復(fù)用及模擬開關(guān)
英文描述： 16-CHANNEL, SGL ENDED MULTIPLEXER, CDFP28
封裝： CERAMIC, FLATPACK-28
文件頁(yè)數(shù)： 3/21頁(yè)
文件大?。?/td> 326K
代理商： 5962R1023701QXC
11
TIMING CHARACTERISTICS (UT16MX117)1,2
(AVDD=5.0V + 0.5V, VDD=3.3V + 0.3V, GND=0V, VDD_IO=3.0V to 5.5V; -55°C < TC < +125°C)
SYMBOL
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
tPROP_S
Propagation delay of analog input
(S[x]) to analog output (COM)
RT=50Ω
CL=50pF
25
ns
tPROP_D
Propagation delay of any changes
in the digital inputs (A[3:0], CS,
PLATCH, SS) affecting the analog
output (COM)
RT=50Ω
CL=50pF
See Figures 5 & 9.
25
140
ns
tMUX
Mux decoding time
RT=50Ω
CL=50pF
See Figures 5 & 9.
50
ns
tBBM
Break-Before-Make-Delay
RT=50Ω
CL=50pF
See Figures 5 & 9.
15
90
ns
tPZLH
Output enable time from HiZ to
Low or High once RESET is
pulled low.
RT=50Ω
CL=50pF
See Figures 7 & 9.
90
ns
tPLHZ
Output disable time from Low or
High to HiZ once RESET is pulled
high.
RT=50Ω
CL=50pF
See Figures 7 & 9.
55
ns
fSCLK
SCLK frequency
RT=50Ω
CL=50pF
See Figures 5 & 9.
2.0
MHz
tH
SCLK high time
RT=50Ω
CL=50pF
See Figures 5 & 9.
190
ns
tL
SCLK low time
RT=50Ω
CL=50pF
See Figures 5 & 9.
190
ns
tSSU
First SCLK setup time (for
shifting window)
RT=50Ω
CL=50pF
See Figures 5 & 9.
5.0
ns
tSSH
Last SCLK hold time (for shifting
window)
RT=50Ω
CL=50pF
See Figures 5 & 9.
10
ns
tSU
Data In (MOSI) setup time
wrt rising edge SCLK
RT=50Ω
CL=50pF
See Figures 5 & 9.
3.0
ns
相關(guān)PDF資料
PDF描述
5962F1023703QXC 16-CHANNEL, SGL ENDED MULTIPLEXER, CDFP28
5962F1023702QXC 16-CHANNEL, SGL ENDED MULTIPLEXER, CDFP28
5962F1023703VXC 16-CHANNEL, SGL ENDED MULTIPLEXER, CDFP28
5962F1023701VXC 16-CHANNEL, SGL ENDED MULTIPLEXER, CDFP28
5962R1023702QXC 16-CHANNEL, SGL ENDED MULTIPLEXER, CDFP28
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