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參數(shù)資料
| 型號： | 5962G9855202VXX |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 16 MHz, RISC MICROCONTROLLER, CPGA144 |
| 封裝： | CERAMIC, PGA-144 |
| 文件頁數(shù)： | 29/64頁 |
| 文件大?。?/td> | 1464K |
| 代理商： | 5962G9855202VXX |
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35
This double-buffering process allows transmitting contiguous
serial data streams. The process of alternately loading the
Transmitter Buffer Register with new data and then reading the
transmitter status from the STATUS register continues until
completion of all serial transmission. An example of UART
transmitter software follows:
WRITE_UART:
INR R11, STATUS
TBR R11, 1DH
BR EQ, WRITE_UART
NOP
INR R15, TXMT
8.2 UART Receiver Operation
The UT69R000’s internal UART has one register associated
with the receive function. This register is the UART Receiver
Buffer Register (RBR). The least significant byte of the RCVR
contains the received serial data. The Status Register contains
error information about the serial data in the receiver. Four
error bits reflect information status, bit 7 (Receiver Error, RE),
which is the logical OR combination of the other three error
bits; bit 6 (Overrun Error, OE); bit 5 (Framing Error, FE); bit
4 (Parity Error, PE). An additional status bit for the Receiver
is the Data Ready (DR) bit. DR is the least significant bit of
the Status Register.
The UT69R000 is ready to receive serial data through the
internal UART, it must poll the Status Register to determine
when the Data Ready (DR) bit transitions from a logical zero
to logical one to signal the UART has indeed received a serial
transmission. When DR equals a logic one, the software reads
the Receiver by executing and Input Register Operation INR
RD, RCVR. The INR instruction takes the eight bits of received
data in the and places this data in the least significant byte of
the destination register (Rd) specified in the instruction.
When the UT69R000 is finished executing the Input Register
Instruction, the software can then determine the validity of the
message by testing the RE bit. After the software has checked
for a valid message, the data is stored. If the UT69R000 is to
receive more data through the UART, the software must return
to polling the Status Register to determine the reception of the
next valid serial transmission. The Input Register Instruction
INR Rd, RCVR clears the DR bit. An example of receiver
software follows:
READ_UART:
INR R11, STATUS
TBR R11, 1FH
BR EQ, READ_UART
NOP
OTR R15, RCVR 9.0
9.0 PROGRAMMING INTERFACE
9.1 Data Formats
The UT69R000 instruction set supports 16-bit integer single-
precision data and 32-bit integer double-precision data. All data
is in 2’s complement representation.
The UT69R000 represents the fixed-point data formats as a 2’s
complement integer with the MSB as the sign bit (figures 30a
and 30b).
Operand Size
The UT69R000’s instruction set supports three operand sizes:
(1) Byte (eight bits); (2) Word (16 bits); and (3) Long Word
(32 bit). Byte operands are only allowed with byte instructions.
All other instructions support word and long-word operands.
Organization of Data in General Purpose Registers
All 20 of the UT69R000’s general purpose data registers
support bit, byte, and word operations. When the system
programmer specifies a byte operation in a specific instruction,
the instruction expects to find the byte of Operand Data in the
least significant eight bits of the data register. The least
significant bit of each of the data registers is bit 0 and the most
significant bit of each of the data registers is bit 15. Any one
of the data registers may be the source or destination for the
operand.
For long-word operands, the UT69R000 organizes the 20
general purpose data registers as 10 even/odd register pairs.
The even-numbered register of the register pair contains the
most significant word. All register pairs may be the source or
destination operands.
14
0
Figure 30a. Single-Precision Fixed-Point Data
Figure 30b. Double-Precision Fixed-Point Data
15
SIGN
DATA
LSB
MSB
SIGN
MSB
LSB
(MSH)
(LSH)
31 30
16 15
0
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