參數(shù)資料
型號(hào)： 5962G9855202VXX
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 16 MHz, RISC MICROCONTROLLER, CPGA144
封裝： CERAMIC, PGA-144
文件頁(yè)數(shù)： 28/64頁(yè)
文件大?。?/td> 1464K
代理商： 5962G9855202VXX
34
7.1.3 Continue Command
The Continue Execution Command allows the user to resume
program execution from the point where the Monitor mode of
operation was entered. The Continue Execution command
takes the form:
C0-Resume execution with Timers A and B halted.
C1- Resume execution with Timer A on and Timer B off.
C2 - Resume execution with Timer A off and Timer B on.
C3- Resume execution with Timers A and B on.
7.1.4 Run Command
The Run From Memory Location Command allows the user to
start program execution from any point within the 1M port
space. This command takes the form Rxxxxn where “xxxxx”
denotes the 20-bit starting address. Valid characters for the
address field (xxxx) are 0-9 and A-F. The value n is either 0,1,2,
or 3 and is defined:
0 - Resume execution with Timers A and B halted.
1 - Resume execution with Timer A on and Timer B off.
2 - Resume execution with Timer A off and Timer B on.
3 - Resume execution with Timers A and B on.
8.0 UART Operation
The UT69R000 has an internal UART. Figure 29 shows a
diagram of the UT69R000 connected to a serial bus. The UART
operates at a fixed frequency of 9600 baud with eight bits, one
stop bit, and odd parity. The idle state for the UART is logic
zero. The TIMCLK input fixes the baud rate of the UART
(9600 baud at TIMCLK equal to 12 MHz). TIMCLK also
controls the frequency of the internal timers (TA and TB). The
status of the UART is read from the System Status Register
(STATUS) bits 7 through 0.
8.1 UART Transmitter Operation
The transmitter portion of the UT69R000’s UART is a double-
buffered configuration consisting of a Transmitter Register and
a Transmitter Buffer Register. The Transmitter Register
contains the serial data stream the UT69R000 is currently
transmitting through the UART; the Transmitter Buffer
Register contains the next message to transmit through the
UART. The system programmer reads the status of the
Transmitter Register from bit 1 (TE) of the Status and the status
of the Transmitter Buffer Register from bit 2 (TBE) of the
Status Register. If bit 2 of the Status register is a logical one,
the UART transmitter buffer is ready for data, once loaded with
data, bit 2 transitions to a logical zero. Bit 1 is a logical zero
during serial transmission and transitions to a logical one when
transmission from the Transmitter Register is complete. The
Status register is read using Input Register Instruction INR
Rd,STATUS.
To initiate a serial data transmission, the system designer must
first load the data to transmit into the Transmitter Buffer
Register with the Output Register Instruction OTR Rd, TXMT.
This instruction loads the least significant byte of the source
register specified in the instruction into the Transmitter Buffer
Register. At this time, TBE goes low and the UT69R000
automatically transfers the data word into the Transmitter
Register. After the transfer is complete, TE goes low and TBE
transition to a logical one indicating a serial transmission is
about to begin and the next data word can be loaded into the
Transmitter Buffer Register.
Figure 29. Serial Data Bus Interface to the UT69R000
AND ODD PARITY
ONE STOP BIT
EIGHT DATA BITS,
9600 BAUD
SERIAL RS-232 BUS X0106-
RCVR
BUS
SERIAL
DRVR
BUS
SERIAL
UT69R000
FOR UART
12 MHz I/P
TIMCLK
UARTIN
UARTOUT
相關(guān)PDF資料
PDF描述
5962H9855201VXC 32-BIT, 12 MHz, RISC MICROCONTROLLER, CPGA144
5962H9855202QXX 32-BIT, 16 MHz, RISC MICROCONTROLLER, CPGA144
5962H9855202VXX 32-BIT, 16 MHz, RISC MICROCONTROLLER, CPGA144
5962R9855201QXA 32-BIT, 12 MHz, RISC MICROCONTROLLER, CPGA144
5962R9855201VXX 32-BIT, 12 MHz, RISC MICROCONTROLLER, CPGA144
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