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參數(shù)資料
| 型號： | 5962G9655501VCC |
| 元件分類： | 計數(shù)器 |
| 英文描述： | ACT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16 |
| 封裝： | SIDE-BRAZED, CERAMIC, DIP-16 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 249K |
| 代理商： | 5962G9655501VCC |
2
FUNCTION TABLE
H = High voltage level h = High voltage level one setup time prior to the low-to-high clock transition
L = Low voltage level l = Low voltage level one setup time prior to the low-to-high clock transition
Notes:
1. The RCO output is high when ENT is high and the counter is at terminal count HHHH.
2. The high-to-low transition of ENP or ENT should only occur while CLK is high for conventional operations.
3. The low-to-high transition of LOAD or CLR should only occur while CLK is high for conventional operations.
LOGIC DIAGRAM
Operating Mode
CLR
CLK
ENP
ENT
LOAD
DATA A,B,C,D
QN
RCO
Reset (Clear)
l
↑
X
L
Parallel Load
h3
↑
X
l
h
L
H
L
1
Count
h3
↑
h
X
Count
1
Inhibit
h3
X
l 2
X
l 2
h3
X
QN
1
L
(2)
(1)
(9)
(7)
(10)
(3)
(4)
(5)
(6)
(14)
(12)
(13)
(11)
(15)
QA
QB
QC
QD
RCO
DATA D
DATA C
DATA B
DATA A
ENT
ENP
LOAD
CLR
CLK
C
D
Q
C
D
Q
C
D
Q
C
D
Q
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