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參數(shù)資料
| 型號(hào)： | 5962G9651403QXC |
| 元件分類： | 門電路 |
| 英文描述： | AC SERIES, QUAD 2-INPUT NOR GATE, CDFP14 |
| 封裝： | CERAMIC, DFP-14 |
| 文件頁數(shù)： | 9/11頁 |
| 文件大小： | 128K |
| 代理商： | 5962G9651403QXC |
7
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%,
as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed
to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density
≤5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765pF/
MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for the maximum radiation dose available for the respective device types.
8. Power dissipation specified per switching output.
9. Parameter guaranteed by design and characterization, but is not tested.
IOH2
High level output current9
VIN = VDD or VSS
VOH = VDD-0.4V
VDD from 3.0V to 3.6V
-6
mA
Ptotal1
Power dissipation 2, 8
CL = 50pF
VDD = 4.5V to 5.5V
1
mW/
MHz
Ptotal2
Power dissipation 2, 8
CL = 50pF
VDD = 3.0V to 3.6V
0.5
mW/
MHz
IDDQ
Quiescent Supply Current
VIN = VDD or VSS
VDD from 3.0V to 5.5V
10
μA
ΔI
DDQ
Quiescent Supply Current Delta
For input under test
VIN = VDD - 2.1V
For all other inputs
VIN = VDD or VSS
VDD = 5.5V
1.6
mA
CIN
Input capacitance 5
= 1MHz
VDD = 0V
15
pF
COUT
Output capacitance 5
= 1MHz
VDD = 0V
15
pF
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