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參數(shù)資料
| 型號： | 5962F9855201QZA |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 12 MHz, RISC MICROCONTROLLER, CQFP132 |
| 封裝： | QFP-132 |
| 文件頁數(shù)： | 2/64頁 |
| 文件大小： | 1464K |
| 代理商： | 5962F9855201QZA |
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10
Pending Interrupt Register
The Pending Interrupt Register (PI) contains information on
pending interrupts attempting to vector the Instruction Counter
Register to a new location. Software or hardware controls the
Pending Interrupt Register contents. Any system interrupt,
when active, sets the corresponding bit in the register. OTR and
INR instruction can also set, clear, and read the Pending
Interrupt Register (figure 11).
Instruction INR Rd, PI stores the PI contents in the destination
register. OTR Rd, PI loads the PI with the contents of the
destination register. OTR Rd, RPI clears the PI register. For
each bit set, to a logic one, in the destination register the
corresponding PI bit is cleared. To clear the PI, first read the
PI, then clear only the bits set to a logic one. Reading, then
clearing the PI prevents the inadvertent clearing of interrupts
occurring during execution of an OTR Rd, RPI command.
Example:
CLEAR: INR Rd, PI
OTR Rd, RPI
To generate a software interrupt clear the corresponding bit in
the PI register before writing to the PI register.
Example:
WRITE: MOV R1, 1000 (hex)
OTR R1, RPI
OTR R1, PI
Note: Do not enable interrupts while the PI is non-zero.
Bit Number
Mnemonic
Description
Bit 15
PWDN
Power Fail
Bit 14
MCHE
Machine Error Interrupt
Bit 13
INT0
External Interrupt 0
Bit 12
USR3
Software Interrupt 3
Bit 11
FIPO
Fix Point Overflow
Bit 10
USR2
Software Interrupt 2
Bit 9
USR1
Software Interrupt 1
Bit 8
TIMA
Timer A Interrupt
Bit 7
INT1
External Interrupt 1
Bit 6
TIMB
Timer B Interrupt
Bit 5
INT2
External Interrupt 2
15 14 13 12 11 10 9
8
7
5
4
3 2
1 0
P
W
D
N
M
C
H
E
I
N
T
O
U
S
R
3
F
I
P
O
U
S
R
2
U
S
R
T
I
M
6
T
I
M
I
N
T
I
N
T
I
N
T
I
N
T
I
N
T
I
N
T
N
/
U
MSB
LSB
Figure 11. The Pending Interrupt Register (PI)
1A
1 B
2
3
5 4
6
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