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參數(shù)資料
| 型號： | 5962F0323601QXX |
| 元件分類： | SRAM |
| 英文描述： | 128K X 32 STANDARD SRAM, 15 ns, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數(shù)： | 15/16頁 |
| 文件大?。?/td> | 297K |
| 代理商： | 5962F0323601QXX |
8
AC CHARACTERISTICS WRITE CYCLE (Pre and Post-Radiation)*
(-55
°C to +125°C for (C) screening and -40°C to +125°C for (W) screening, V
DD1 = VDD1 (min), VDD2 = VDD2 (min))
Notes:
* Post-radiation performance guaranteed at 25
°C per MIL-STD-883 Method 1019.
1. Tested with G high.
2. Three-state is defined as 200mV change from steady-state output voltage.
SYMBOL
PARAMETER
8R128K32-15
MIN
MAX
UNIT
tAVAV
1
Write cycle time
15
ns
tETWH
Device enable to end of write
12
ns
tAVET
Address setup time for write (E1/E2- controlled)
0
ns
tAVWL
Address setup time for write (W - controlled)
1
ns
tWLWH
Write pulse width
12
ns
tWHAX
Address hold time for write (W - controlled)
2
ns
tEFAX
Address hold time for device enable (E1/E2- controlled)
2
ns
tWLQZ
2
W - controlled three-state time
5
ns
tWHQX
2
W - controlled output enable time
4
ns
tETEF
Device enable pulse width (E1/E2 - controlled)
12
ns
tDVWH
Data setup time
7
ns
tWHDX
Data hold time
2
ns
tWLEF
Device enable controlled write pulse width
12
ns
tDVEF
Data setup time
7
ns
tEFDX
Data hold time
2
ns
tAVWH
Address valid to end of write
12
ns
tWHWL
1
Write disable time
3
ns
tBLWH
LHWE, HHWE low to write high
12
ns
tBLEF
LHWE, HHWE low to enable high
12
ns
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