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參數(shù)資料
| 型號： | 5962-9320301MEA |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 多路復(fù)用及模擬開關(guān) |
| 英文描述： | 4-CHANNEL, SGL ENDED MULTIPLEXER, CDIP16 |
| 封裝： | CERDIP-16 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 1306K |
| 代理商： | 5962-9320301MEA |
http://www.national.com
6
above 1/2 the sampling frequency will be aliased into
the baseband and will corrupt the signal of interest.
When the CLC533 is switched from one channel to
another, the output slews rapidly until it arrives at
the new signal. This high slew rate signal can capac-
itively couple into other nodes in the circuit and can
have a detrimental effect on overall performance.
Since
coupling
through
stray
capacitance
and
inductances decreases with decreasing dV/dt, the
slew rate should be minimized consistent with system
throughput requirements.
Figure 1: ECL Level Channel SELECT Configuration
Figure 2: TTL/CMOS Level Channel
SELECT Configuration
Output Load
The final frequency response that is realized is a result of
both the compensation capacitor and the load that the
CLC533 is driving. Figure 3 below shows the effect that
CCOMP has on bandwidth for a fixed load. Graphs on the
preceding pages demonstrate the effect of CCOMP on
pulse response and settling time, and the optimum value
of CCOMP to maximize bandwidth for various amounts of
resistive loading. Because there are so many factors that
go into determining the optimum value of CCOMP it is
recommended that once a value is selected, the
application circuit be built up and larger and smaller
compensation capacitors be tried to determine the best
value for that particular circuit.
The output load that the CLC533 is driving has an effect
on the harmonic distortion of the device as well as
frequency response. Distortion is minimized with a 500
load. When driving components with a high input
impedance, addition of a load resistor can improve the
performance. If the load is capacitive in nature, it should
be isolated from the CLC533 output via a series resistor.
The recommended series resistor Rs, for various
capacitive loads CL, can be found by referring to the
“Recommended Compensation Cap vs. Load” plot in the
“Typical Performance” section.
Figure 3
Power Supplies and Grounding
In
any
circuit
there
are
connections
between
components that are not desired. Some of the most com-
mon of these are the connections made through the
power supply and grounding network. The goal in laying
out the power and ground network for a mixed mode
circuit is to minimize the impedance from the power pins
to the supply, and minimize the impedance of the ground
network.
To minimize impedance of the ground and power nets,
use the heaviest possible traces and ground planes for
minimizing the DC impedance. To further reduce the
supply impedance at higher frequencies, a 6 to 10
F
capacitor should be placed between supply lines and
ground. At very high frequencies, the inductance in the
traces becomes significant and 0.01 to 0.1
F bypass
capacitors need to be placed as close to each power pin
as is practical. To reduce the negative effects of ground
impedances that will exist, consider the paths that ground
currents must take to get from the various devices on the
circuit card to the power supply. To achieve good system
performance, it is vital that large currents and high-speed
time varying currents like CMOS signals, be kept away
from precision analog components. This can be achieved
through layout of the power and ground nets. Using a
ground plane split between analog and digital sections of
the circuit forces all of the ground current from the digital
circuits to go directly to the power connector without
straying to the analog side of the card.
Optimizing for Channel-to-Channel Isolation
Although
the
CLC533
has
excellent
channel-to-
channel isolation, if there is cross talk between the input
signals
before
they
reach
the
CLC533,
the
multiplexer will faithfully pass these corrupted signals
through to its output and dutifully take the blame for poor
Small Signal Bandwidth (30MHz/div)
50
50
81
130
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 5962-9320401MEA | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 12-BIT DACPORT RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| 5962-9321101MCA | 功能描述:總線接收器 RoHS:否 制造商:Texas Instruments 接收機數(shù)量:4 接收機信號類型:Differential 接口類型:EIA/TIA-422-B, V.11 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-16 封裝:Reel |
| 5962-9321201MPA | 制造商:Linear Technology 功能描述:SMD (STD. MIL DWG.) LT1111MJ8 |
| 5962-9321401MEA | 制造商:Analog Devices 功能描述:V-Ref Programmable 制造商:Analog Devices 功能描述:V-Ref Programmable ±10V 10mA 16-Pin CDIP Tube 制造商:Analog Devices 功能描述:V-REF PROGRAMMABLE 10V 10MA 16CDIP - Rail/Tube 制造商:Analog Devices Inc. 功能描述:Voltage & Current References IC MONO +/-10V REFERENCE 制造商:Analog Devices Inc. 功能描述:IC MONO +/-10V REFERENCE |
| 5962-9321601QPA | 制造商:Texas Instruments 功能描述:OP Amp Single GP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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